parti-wave/TAV_RGC_World_DiscoverPhysics

TAV RGC World — Deterministic 49-Core Logistic Lattice

A hardware-characterized, finite-precision logistic-map lattice (49 parallel Q1.31 iterators) on an Artix-7 FPGA

This world definition provides a realistic computational substrate based on actual FPGA telemetry from the logistic_bank core on the Arty A7-100T. It implements a 49-core synchronous logistic-map lattice in Q1.31 fixed-point arithmetic (32-bit recurrent state per core), with per-core r values spanning [3.5, 4.0] to tile the period-doubling route to chaos. The state is telemetered as its top 24 bits (x_value[31:8]); the low 8 bits are retained on-chip but not transmitted.

What This World Represents

Unlike purely theoretical or software-simulated worlds, this definition is grounded in measured hardware behavior from multiple independent cold-start runs (N1, N2, N3, N4).

Key measured properties:

• 16 cores have periods short enough to be exactly resolved within the original characterization window and faithfully through the 24-bit telemetry.
• 33 cores have periods that are only lower bounds, for two compounding reasons: (a) their true period in the 32-bit Q1.31 state space exceeds the observation window, and (b) the 24-bit export drops the low 8 state bits, so an apparent repeat in telemetry is not a confirmed period (distinct 32-bit states can share the same top 24 bits). The partition is therefore an observation/telemetry-resolvability property, not a structural feature of the dynamics. This caveat is no longer hypothetical: see the Core 04 case study below for a measured instance.
• Strict data integrity: only frames with delta_n = 49 are accepted. The iteration counter n is telemetered at full 32-bit width, so the integrity accounting is exact and unaffected by the x truncation.
• Computation is reproducible across independent runs at the telemetered 24-bit x observable (and at full precision for n).

Key Features

• 49-core deterministic logistic lattice (r_k = 3.500 + k/96)
• Real telemetry-derived period information for all cores
• Clear separation between resolved and projected cores
• Built-in integrity rule enforcement (delta_n = 49)
• Multi-run provenance: N1–N3 characterization lineage plus N4, a 30-day endurance reference run (2026-06-06 → 2026-07-06)
• Bit-exact software twin of the FPGA datapath, validated against captured orbits
• Accompanying Python loader and analysis tools

Reproducibility — scope of the claim

Reproducibility is asserted for the telemetered x observable (top 24 bits of the 32-bit Q1.31 state) and for the full-width n counter. The recurrent state is 32 bits; the export transmits the high 24 of those bits and drops the low 8 (noise-dominated). Identical cold-start runs therefore reproduce the same telemetered x sequences bit-for-bit, but this is reproducibility of the 24-bit observable, not a claim about the 8 untransmitted state bits. This is the strongest statement the telemetry can support, and it is the one made here.

Data Integrity and the Capture-Onset Transient

Frame integrity is enforced by a single rule: only frames carrying a global iteration delta of exactly delta_n = 49 are accepted.

Steady-state frame corruption is zero. All rejected frames occur during the capture-onset framer-lock transient — the interval before byte/frame alignment is acquired on the free-running UART stream — and they never recur once lock is established. The FPGA emits frames continuously and does not wait for the host; when the host attaches, it drops into a live stream with pre-existing bytes in the transmit FIFO and OS serial buffer. Until two consecutive sequence-numbered frames produce a valid delta_n = 49, each misaligned read fails the integrity test and is rejected. Once lock is acquired it is retained for the remainder of the capture.

Empirically the transient is a fixed-depth flush: exactly 49 frames are rejected in every characterized run (N1, N2, N3), independent of capture length — one rejected frame per core, consistent with a single stale 49-core readout sweep being cleared before lock. The count does not scale with run length, which is the signature of a one-time onset event rather than ongoing loss. (N4's final onset/malformed tally is recorded in its end-of-run session summary.)

These onset frames are excised by the integrity rule at the loader, not by modifying the instrument during a live capture. A rejected frame appearing after lock would be a genuine anomaly; none has been observed across N1–N4.

N4 Endurance Run and the 2²⁴ Carry Crossing

N4 is a continuous 30-day, 0-hour capture (start 2026-06-06 14:59:47, scheduled end 2026-07-06 14:59:47; ~18.1 million frames at 7.000 frames/s), serving as the current reference run.

On 2026-07-04 the global iteration counter crossed n = 16,777,216 (2²⁴, 0x01000000) live, mid-capture. A witness-grade audit of the crossing window (±5,000 frames) recorded:

• Zero delta_n ≠ 49 events across 10,001 examined rows.
• 49/49 cores with a clean delta_n = 49 straddle across the carry.
• The exact carry row logged by core 08 — as required by the round-robin arithmetic (2²⁴ mod 49 = 8).
• All short-period cores' orbit value sets bit-identical before and after the carry.

The carry is an ordinary increment of the full-width 32-bit counter; the crossing audit confirms in captured data what the RTL states by construction. No state, framing, or integrity effect of any kind is associated with the 2²⁴ boundary.

Additionally, N4 shows zero detectable state upsets over the full run — including on the core most sensitive to perturbation (see below) — i.e., no single-event upsets are visible in the witness across ~30 days of continuous operation.

Telemetry Resolution Case Study: Core 04

Core 04 (r = 3.5416̄, the lattice's closest core to the period-4 → 8 bifurcation at r ≈ 3.5441) provides a measured demonstration of why telemetry resolution must be stated explicitly:

• The ideal real-arithmetic map at this r is period-4.
• The core's true 32-bit quantized cycle is period-8 (verified by the bit-exact software twin): the fixed-point lattice locks onto a closed 8-cycle shadowing the ideal 4-cycle, with doubled pairs split at the least-significant-bit scale — the imminent bifurcation expressed ~0.0024 early in r by quantization.
• At the 24-bit telemetry level this appears as 6 distinct codes: two of the four orbit positions resolve into LSB-adjacent code pairs; the other two pairs are split more finely than one 24-bit quantum and share single codes.
• At 6-decimal normalized precision (x_norm) it appears as 4 distinct values — the code pairs collapse.

One deterministic orbit; three observation resolutions; three different apparent periods, each correct at its own scale. Exact-period analysis of this dataset should therefore be performed on x_raw24 (or the twin's full 32-bit state), never on x_norm. The distinct-code count for core 04 is constant (6) from the end of the initial transient (~frame 200,000) through the full run — the structure is deterministic shadowing, not drift or upset.

Bit-Exact Software Twin

The repository includes a software twin replicating the FPGA datapath operation-for-operation (Q1.31 multiply, truncating slice [62:31]; Q2.30 × Q1.31 multiply, truncating slice [61:30]). The twin has been validated against captured hardware orbits at exact precision, including the non-obvious core 04 period-8 cycle (all six 24-bit codes predicted and matched). It enables pre-silicon prediction of orbit content for firmware revisions.

Current Status

• N4 (~18.1M frames, 30 days) is the current reference run, superseding N2 (4M frames).
• Cross-run determinism is verified bit-for-bit: independent cold-start runs reproduce identical telemetered sequences (24-bit x, full-width n) over their full common prefix (N1 ≡ N2 ≡ N3 ≡ N4).
• The 2²⁴ counter carry has been crossed in-capture and audited: non-event (see above).
• The resolved/projected partition is reproducible across runs. Because the partition reflects which periods fit the observation window (in a 32-bit state space, ceiling ~2³² ≈ 4.3e9 per core), longer runs can promote a core to "resolved" only if its true period falls within the newly observable range; cores remaining "projected" indicate periods exceeding the window — an observation limit, not a structural bound.
• Planned (N5): a single-constant firmware revision retuning core 12's r word to the primary superstable period-6 parameter (r = 3.627557529515524, Q2.30 32'hE829E70E), with predicted orbit content pinned in advance by the software twin.

Full methods and analysis are documented in the accompanying tav_rgc_world.yaml and supporting scripts.

Files Included

• tav_rgc_world.yaml — Core world definition (v1.1)
• tav_rgc_world.py — Python loader
• example_load_run.py — Example loader with integrity filtering
• compare_all_runs.py — Comparison tool across runs (N1–N4)
• rgc_integrity.py — Capture-onset lock detection and frame partitioning
• rgc_period_census_v1.py — Exact-period census over a capture tail
• n4_crossing_certificate.py — 2²⁴ carry-crossing witness audit
• core04_twin_check.py — Core 04 quantized-cycle verification (twin vs. capture)
• README.md — Usage documentation

Quick Start

from tav_rgc_world import RGCWorld

world = RGCWorld("tav_rgc_world.yaml")
print(world.summary())

resolved = world.get_resolved_cores()
projected = world.get_projected_cores()