HPAI-BSC/Qwen3.6-27B-RL-Verif
Text Generation • 27B • Updated • 2
Datasets:
prompt stringlengths 450 62.1k | response stringlengths 1.28k 36.6k | top_module stringlengths 1 104 | instance stringlengths 2 109 |
|---|---|---|---|
Read the SystemVerilog module `altera_up_video_decoder_add_endofpacket` below and write a markdown test plan that a verification engineer could use to author a testbench for it.
```verilog
module altera_up_video_decoder_add_endofpacket (
clk,
reset,
stream_in_data,
stream_in_startofpacket,
stream_in_endofpacket... |
<think>
* Module Name: `altera_up_video_decoder_add_endofpacket`
* Inputs: `clk`, `reset`, `stream_in_data`, `stream_in_startofpacket`, `stream_in_endofpacket`, `stream_in_valid`, `stream_out_ready`.
* Outputs: `stream_in_ready`, `stream_out_data`, `stream_out_startofpacket`, `stream_out_endofpacket`, `s... | altera_up_video_decoder_add_endofpacket | altera_up_video_decoder_add_endofpacket_verif_tb |
Read the SystemVerilog module `final_project_mm_interconnect_0_cmd_demux` below and write a markdown test plan that a verification engineer could use to author a testbench for it.
```verilog
// (C) 2001-2018 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and ot... |
<think>
* Module Name: `final_project_mm_interconnect_0_cmd_demux`
* Purpose: Demultiplexer for command data based on a one-hot channel signal.
* Inputs: `clk`, `reset`, `sink_valid`, `sink_data` (107 bits), `sink_channel` (13 bits), `sink_startofpacket`, `sink_endofpacket`, and 13 `srcX_ready` signals.
... | final_project_mm_interconnect_0_cmd_demux | dut |
Read the SystemVerilog module `accelerator_design` and the test plan below, then write a complete self-checking SystemVerilog testbench for it.
```verilog
////////////////////////////////////////////////////////////////////////////////
// __ _ _ _ //
//... |
<think>
* DUT: `accelerator_design`.
* Functionality: 8-bit unsigned adder with a 9-bit registered output.
* Inputs: `clk`, `rst` (async active-high), `in1` [7:0], `in2` [7:0].
* Output: `out` [8:0].
* Reset: Asynchronous, forces `out` to 0.
* Clock: Rising edge triggers addition. Outpu... | accelerator_design | accelerator_design_verif_tb |
Read the SystemVerilog module `Decoder` and the test plan below, then write a complete self-checking SystemVerilog testbench for it.
```verilog
module Decoder (
input [2:0] inpt,
input enb, // Enable
output reg [7:0] out
);
always @(*) begin
if (enb) begin
case (inpt)
3'b0... |
<think>
* DUT: `Decoder` (3-to-8 line decoder with enable).
* Functionality:
* `enb = 1`: `out = (1 << inpt)`.
* `enb = 0`: `out = 0`.
* Requirements:
* Self-checking.
* Follow the provided Test Plan.
* Compatibility with `iverilog -g2012` (no classes, no... | Decoder | tb |
Read the SystemVerilog module `som_system_altera_merlin_demultiplexer_180_uoxykti` below and write a markdown test plan that a verification engineer could use to author a testbench for it.
```verilog
// (C) 2001-2018 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functio... |
<think>
* Module Name: `som_system_altera_merlin_demultiplexer_180_uoxykti`
* Purpose: A demultiplexer for a streaming interface. It takes a single input stream (sink) and routes it to one of two output streams (src0 or src1) based on a `sink_channel` one-hot signal.
* Parameters: `ST_DATA_W` = 108, `ST_... | som_system_altera_merlin_demultiplexer_180_uoxykti | tb_top |
Read the SystemVerilog module `ALU` below and write a markdown test plan that a verification engineer could use to author a testbench for it.
```verilog
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2021/03/10 19:0... |
<think>
Expert SystemVerilog Verification Engineer.
`ALU` module (combinational).
* `a` (32-bit), `b` (32-bit), `alucount` (3-bit).
* `res` (32-bit), `zero` (1-bit).
* Operation Mapping:
* `000`: AND (`a & b`)
* `001`: OR (`a | b`)
* `010`: ADD (... | ALU | dut |
Read the SystemVerilog module `accelerator_design` below and write a markdown test plan that a verification engineer could use to author a testbench for it.
```verilog
////////////////////////////////////////////////////////////////////////////////
// __ _ _ _ ... |
<think>
* Module name: `accelerator_design`.
* Inputs: `clk`, `rst` (asynchronous reset, active high), `in1` [7:0], `in2` [7:0].
* Output: `out` [8:0].
* Logic: On `posedge clk`, `out <= in1 + in2`. On `posedge rst`, `out <= 0`.
* Functionality: A simple registered 8-bit adder with a 9-bit ou... | accelerator_design | accelerator_design_test |
Read the SystemVerilog module `ntm_design` below and write a markdown test plan that a verification engineer could use to author a testbench for it.
```verilog
////////////////////////////////////////////////////////////////////////////////
// __ _ _ _ ... |
<think>
* Top Module: `ntm_design`
* Inputs: `clk` (1 bit), `rst` (1 bit), `in1` (8 bits), `in2` (8 bits).
* Outputs: `out` (9 bits).
* Behavior:
* Asynchronous reset (`posedge rst`): `out` is reset to 0.
* Clocked logic (`posedge clk`): `out` is the sum of `in1` and `in2`.
... | ntm_design | ntm_design_test |
Read the SystemVerilog module `dMUL_uni` and the test plan below, then write a complete self-checking SystemVerilog testbench for it.
```verilog
module dMUL_uni (
input logic clk, // Clock
input logic rst_n, // Asynchronous reset active low
input logic [7:0] iA,
input logic [7:0] iB,
input logi... |
<think>
* Module: `dMUL_uni`
* Inputs: `clk`, `rst_n`, `iA [7:0]`, `iB [7:0]`, `loadA`, `loadB`, `sobolSeqA [7:0]`, `sobolSeqB [7:0]`.
* Output: `oC`.
* Logic:
* `iA_buf` and `iB_buf` are clocked registers.
* `iA_buf` updates if `loadA == 1`.
* `iB_buf` updates if `loa... | dMUL_uni | tb_dMUL_uni |
Read the SystemVerilog module `STD_WRAP_CKINV` and the test plan below, then write a complete self-checking SystemVerilog testbench for it.
```verilog
// ----------------------------------------------------------------------
// Copyright 2024 TimingWalker
//
// Licensed under the Apache License, Version 2.0 (the "Lice... |
<think>
* DUT: `STD_WRAP_CKINV` (Simple Inverter).
* Interface: `in_i` (input), `zn_o` (output).
* Functionality: `zn_o = ~in_i`.
* Test Plan requirements:
* Reference model: `expected_zn_o = ~in_i`.
* Invariants: `zn_o === ~in_i`.
* Scenarios: Logic Low (0), Logic Hig... | STD_WRAP_CKINV | tb |
Read the SystemVerilog module `top_module` and the test plan below, then write a complete self-checking SystemVerilog testbench for it.
```verilog
module top_module (
input clk,
input reset,
input [3:0] A,
input [3:0] B,
input load,
input shift,
output [3:0] final_output
);
// Ripple C... |
<think>
* DUT: `top_module` (XOR logic via `ripple_carry_adder`, Shift-Left register with Parallel Load and Async Reset, Final Output is XOR result + register value).
* XOR Logic: `adder_output = A ^ B`.
* Register Priority: Reset (Async) > Load (Sync) > Shift (Sync) > Hold.
* Final Output: `final_... | top_module | uut |
Read the SystemVerilog module `bin2bcd` below and write a markdown test plan that a verification engineer could use to author a testbench for it.
```verilog
module bin2bcd (
input [4:0] BIN,
output reg [3:0] BCD0,
output reg [3:0] BCD1
);
reg [3:0] temp_bcd0;
reg [3:0] temp_bcd1;
reg [4:0] temp_bin;
alw... |
<think>
* Module: `bin2bcd`
* Inputs: `BIN [4:0]` (5-bit unsigned integer). Range: 0 to 31 ($2^5 - 1$).
* Outputs: `BCD0 [3:0]`, `BCD1 [3:0]`.
* Logic: Combinational. `BCD0` is the ones digit (BIN % 10), `BCD1` is the tens digit (BIN / 10 % 10).
* Design Detail: Uses blocking assignments in a... | bin2bcd | bin2bcd_test |
Read the SystemVerilog module `reg32` below and write a markdown test plan that a verification engineer could use to author a testbench for it.
```verilog
module reg32 (clk, reset, d_in, d_out);
input clk, reset;
input [31:0] d_in;
output [31:0] d_out;
reg [31:0] d_out;
always @(pose... |
<think>
* DUT: `reg32`
* Function: A 32-bit register with synchronous reset.
* Inputs: `clk`, `reset`, `d_in` (32-bit).
* Outputs: `d_out` (32-bit).
* Behavior:
* On `posedge clk`:
* If `reset == 1`, `d_out` becomes 0.
* Else, `d_out` becomes `d_in`.
... | reg32 | test_reg32 |
Read the SystemVerilog module `soc_system_mm_interconnect_2_cmd_mux` and the test plan below, then write a complete self-checking SystemVerilog testbench for it.
```verilog
// (C) 2001-2016 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software a... |
<think>
* DUT: `soc_system_mm_interconnect_2_cmd_mux`.
* Functionality: A 1:1 combinational passthrough.
* Interfaces:
* Sink 0: `sink0_valid`, `sink0_data[117:0]`, `sink0_channel[1:0]`, `sink0_startofpacket`, `sink0_endofpacket`, `sink0_ready` (output).
* Src: `src_valid`, `src_data[... | soc_system_mm_interconnect_2_cmd_mux | tb_top |
Read the SystemVerilog module `and_module` and the test plan below, then write a complete self-checking SystemVerilog testbench for it.
```verilog
module nor_gate (
input a,
input b,
output out
);
wire nand1, nand2;
nand n1(nand1, a, b);
nand n2(nand2, a, b);
nand n3(out, nand1, nand2);
en... |
<think>
* DUT: `and_module`.
* Functionality: Simple 2-input AND gate.
* Inputs: `a` (1 bit), `b` (1 bit).
* Output: `out` (1 bit).
* Test Plan requirements: Exhaustive truth table (4 cases), reference model (`expected_out = (a && b)`), self-checking, compatible with `iverilog -g2012`.
*... | and_module | tb |
Read the SystemVerilog module `MISTRAL_CLKBUF` and the test plan below, then write a complete self-checking SystemVerilog testbench for it.
```verilog
module MISTRAL_IB((* iopad_external_pin *) input PAD, output O);
assign O = PAD;
endmodule
module MISTRAL_OB((* iopad_external_pin *) output PAD, input I);
assign ... |
<think>
* DUT: `MISTRAL_CLKBUF` (Simple combinational buffer: `Q = A`).
* Goal: Complete, self-checking SystemVerilog testbench.
* Compliance: `iverilog -g2012` (limited subset).
* Constraints:
* No classes/constraints/covergroups (not supported by simple `iverilog` versions usually, or r... | MISTRAL_CLKBUF | MISTRAL_CLKBUF_test |
End of preview. Expand in Data Studio
SystemVerilog SFT
85,701 examples for supervised fine-tuning on design verification: test-plan generation from RTL and self-checking SystemVerilog testbench generation conditioned on RTL and a test plan.
The dataset distills Gemma-4-31B teacher responses, including reasoning, generated at scale using vLLM with 8 data-parallel replicas across 32 H100 GPUs. Each retained DUT/test-plan/testbench triplet has an associated testbench that compiled and passed on the reference DUT.
🤗 Models
🤗 Datasets
- SystemVerilog-SFT-86k ← you are here
- SystemVerilog-RL-12k
Structure
Each line of train.jsonl contains four fields, in this order:
| Field | Description |
|---|---|
prompt |
RTL → Test-Plan and (RTL, Test-Plan) → Testbench. |
response |
Gemma-4-31B teacher response, including reasoning and the generated test plan or testbench. |
top_module |
DUT module name. |
instance |
DUT instance name in the testbench. |
Sources and filtering
The table below describes the sources for SystemVerilog snippets used for data generation
| Filtering stage | The Stack v1 | The Stack v2 | MetRex | Our GitHub Crawl | Total |
|---|---|---|---|---|---|
| Collected snippets | 100,755 | 310,867 | 25,868 | 439,561 | 877,051 |
| After license filtering | 99,096 | 59,755 | 25,868 | 439,561 | 624,280 |
| Under 16k tokens | 97,739 | 58,160 | 25,703 | 433,012 | 614,614 |
Compiles with iverilog -g2012 |
17,298 | 12,145 | 24,505 | 60,744 | 114,692 |
| Top module and ports extracted | 12,496 | 8,373 | 22,711 | 41,008 | 84,588 |
After multiple rounds of inference, our teacher model produced 43,974 validated (DUT, test-plan, testbench) triplets, resulting in 87,948 SFT examples across the two tasks: test-plan generation and testbench generation.
Decontamination
The dataset was decontaminated against VerilogEval v2.0, RTLLM v2.1, and CVDP v1.1.0 Heavy Agentic tasks, harnesses, and public RTL repository context, using normalized exact and fuzzy code matching, with prompts and descriptions checked separately.
Citation
% Pending TODO
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