task_id stringlengths 16 24 | shuttle_name stringclasses 7 values | project_name stringlengths 12 79 | task_name stringlengths 7 59 | top_module_name stringlengths 9 54 | system_message stringclasses 1 value | prompt stringlengths 724 368k | golden_module stringlengths 66 320k |
|---|---|---|---|---|---|---|---|
ttsky25a-finale_1101 | ttsky25a-finale | tapeoutcutm-High-Speed-8-8-Vedic-Multiplier-for-Efficient-Arithmetic-Operations | task_tt_um_vedic_4x4 | tt_um_vedic_4x4 | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region. | module tt_um_vedic_4x4 (
input [7:0] ui_in, // ui_in[3:0] = a, ui_in[7:4] = b
output [7:0] uo_out, // r = a × b
input [7:0] uio_in, // unused
output [7:0] uio_out, // unused
output [7:0] uio_oe, // unused
input clk, // unused
input rst_n, // unused
input ena // unused
);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
module vedic4 (
input [3:0] a,
input [3:0] b,
output [7:0] r
);
wire [3:0] p0, p1, p2, p3;
wire [7:0] temp1, temp2, temp3;
vedic2 v0 (a[1:0], b[1:0], p0);
vedic2 v1 (a[3:2], b[1:0], p1);
vedic2 v2 (a[1:0], b[3:2], p2);
vedic2 v3 (a[3:2], b[3:2], p3);
assign temp1 = {4'b0000, p1} << 2;
assign temp2 = {4'b0000, p2} << 2;
assign temp3 = {p3, 4'b0000};
assign r = p0 + temp1 + temp2 + temp3;
endmodule
module vedic2 (
input [1:0] a,
input [1:0] b,
output [3:0] r
);
wire p0, p1, p2, p3;
wire s1, c1, s2, c2;
assign p0 = a[0] & b[0];
assign p1 = a[1] & b[0];
assign p2 = a[0] & b[1];
assign p3 = a[1] & b[1];
assign s1 = p1 ^ p2;
assign c1 = p1 & p2;
assign s2 = p3 ^ c1;
assign c2 = p3 & c1;
assign r[0] = p0;
assign r[1] = s1;
assign r[2] = s2;
assign r[3] = c2;
endmodule
| module tt_um_vedic_4x4 (
input [7:0] ui_in, // ui_in[3:0] = a, ui_in[7:4] = b
output [7:0] uo_out, // r = a × b
input [7:0] uio_in, // unused
output [7:0] uio_out, // unused
output [7:0] uio_oe, // unused
input clk, // unused
input rst_n, // unused
input ena // unused
);
assign uio_out = 8'b0;
assign uio_oe = 8'b0;
wire [3:0] a = ui_in[3:0];
wire [3:0] b = ui_in[7:4];
wire [7:0] r;
vedic4 v4 (
.a(a),
.b(b),
.r(r)
);
assign uo_out = r;
endmodule |
ttsky25a-finale_1102 | ttsky25a-finale | tapeoutcutm-High-Speed-8-8-Vedic-Multiplier-for-Efficient-Arithmetic-Operations | task_vedic2 | tt_um_vedic_4x4 | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region. | module tt_um_vedic_4x4 (
input [7:0] ui_in, // ui_in[3:0] = a, ui_in[7:4] = b
output [7:0] uo_out, // r = a × b
input [7:0] uio_in, // unused
output [7:0] uio_out, // unused
output [7:0] uio_oe, // unused
input clk, // unused
input rst_n, // unused
input ena // unused
);
assign uio_out = 8'b0;
assign uio_oe = 8'b0;
wire [3:0] a = ui_in[3:0];
wire [3:0] b = ui_in[7:4];
wire [7:0] r;
vedic4 v4 (
.a(a),
.b(b),
.r(r)
);
assign uo_out = r;
endmodule
module vedic4 (
input [3:0] a,
input [3:0] b,
output [7:0] r
);
wire [3:0] p0, p1, p2, p3;
wire [7:0] temp1, temp2, temp3;
vedic2 v0 (a[1:0], b[1:0], p0);
vedic2 v1 (a[3:2], b[1:0], p1);
vedic2 v2 (a[1:0], b[3:2], p2);
vedic2 v3 (a[3:2], b[3:2], p3);
assign temp1 = {4'b0000, p1} << 2;
assign temp2 = {4'b0000, p2} << 2;
assign temp3 = {p3, 4'b0000};
assign r = p0 + temp1 + temp2 + temp3;
endmodule
module vedic2 (
input [1:0] a,
input [1:0] b,
output [3:0] r
);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
| module vedic2 (
input [1:0] a,
input [1:0] b,
output [3:0] r
);
wire p0, p1, p2, p3;
wire s1, c1, s2, c2;
assign p0 = a[0] & b[0];
assign p1 = a[1] & b[0];
assign p2 = a[0] & b[1];
assign p3 = a[1] & b[1];
assign s1 = p1 ^ p2;
assign c1 = p1 & p2;
assign s2 = p3 ^ c1;
assign c2 = p3 & c1;
assign r[0] = p0;
assign r[1] = s1;
assign r[2] = s2;
assign r[3] = c2;
endmodule |
ttsky25a-finale_1103 | ttsky25a-finale | tapeoutcutm-High-Speed-8-8-Vedic-Multiplier-for-Efficient-Arithmetic-Operations | task_vedic4 | tt_um_vedic_4x4 | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region. | module tt_um_vedic_4x4 (
input [7:0] ui_in, // ui_in[3:0] = a, ui_in[7:4] = b
output [7:0] uo_out, // r = a × b
input [7:0] uio_in, // unused
output [7:0] uio_out, // unused
output [7:0] uio_oe, // unused
input clk, // unused
input rst_n, // unused
input ena // unused
);
assign uio_out = 8'b0;
assign uio_oe = 8'b0;
wire [3:0] a = ui_in[3:0];
wire [3:0] b = ui_in[7:4];
wire [7:0] r;
vedic4 v4 (
.a(a),
.b(b),
.r(r)
);
assign uo_out = r;
endmodule
module vedic4 (
input [3:0] a,
input [3:0] b,
output [7:0] r
);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
module vedic2 (
input [1:0] a,
input [1:0] b,
output [3:0] r
);
wire p0, p1, p2, p3;
wire s1, c1, s2, c2;
assign p0 = a[0] & b[0];
assign p1 = a[1] & b[0];
assign p2 = a[0] & b[1];
assign p3 = a[1] & b[1];
assign s1 = p1 ^ p2;
assign c1 = p1 & p2;
assign s2 = p3 ^ c1;
assign c2 = p3 & c1;
assign r[0] = p0;
assign r[1] = s1;
assign r[2] = s2;
assign r[3] = c2;
endmodule
| module vedic4 (
input [3:0] a,
input [3:0] b,
output [7:0] r
);
wire [3:0] p0, p1, p2, p3;
wire [7:0] temp1, temp2, temp3;
vedic2 v0 (a[1:0], b[1:0], p0);
vedic2 v1 (a[3:2], b[1:0], p1);
vedic2 v2 (a[1:0], b[3:2], p2);
vedic2 v3 (a[3:2], b[3:2], p3);
assign temp1 = {4'b0000, p1} << 2;
assign temp2 = {4'b0000, p2} << 2;
assign temp3 = {p3, 4'b0000};
assign r = p0 + temp1 + temp2 + temp3;
endmodule |
ttsky25a-finale_1104 | ttsky25a-finale | tapeoutcutm-UART-protocol | task_tt_um_uart | tt_um_uart | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region. | `default_nettype none //
module tt_um_uart (
input wire [7:0] ui_in, // control inputs
output wire [7:0] uo_out, // received data
input wire [7:0] uio_in, // tx_data (bits 7:1), rx_data (bit 0)
output wire [7:0] uio_out, // tx line + interrupt flags
output wire [7:0] uio_oe, // output enable
input wire ena, // always 1
input wire clk, // main clock
input wire rst_n // active low reset
);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
`default_nettype none //
module uart_top #(
parameter WIDTH = 8
)(
input wire clk,
input wire clk_sel,
input wire rstn,
input wire tr_en,
input wire mode_osl,
input wire [15:0] dlh_dll,
input wire [6:0] tr_fifo_data_w,
input wire rx_data_in,
output wire tx_data_out,
output wire [7:0] rx_data_read_out,
input wire rx_data_read_en,
input wire tx_data_w_en,
output wire transmit_busy,
output wire tx_i_interpt,
output wire rx_i_interpt,
output wire tx_o_interpt,
output wire rx_o_interpt,
input wire tr_data_load
);
// Internal signals
reg [7:0] rx_data_reg;
reg [7:0] tx_data_reg;
reg [3:0] tx_bit_counter;
reg [3:0] rx_bit_counter;
reg [15:0] baud_counter;
reg [15:0] baud_limit;
reg tx_active;
reg rx_active;
reg tx_line_reg;
reg rx_data_ready;
reg tx_fifo_empty;
reg rx_fifo_full;
// State machine states
localparam IDLE = 2'b00;
localparam START = 2'b01;
localparam DATA = 2'b10;
localparam STOP = 2'b11;
reg [1:0] tx_state;
reg [1:0] rx_state;
reg [1:0] rx_state_prev;
// Baud rate generation
always @(posedge clk or negedge rstn) begin
if (!rstn) begin
baud_counter <= 0;
baud_limit <= dlh_dll;
end else begin
if (clk_sel) begin
baud_limit <= 16'h0001; // Full clock rate
end else begin
baud_limit <= dlh_dll; // Divided clock rate
end
if (baud_counter >= baud_limit) begin
baud_counter <= 0;
end else begin
baud_counter <= baud_counter + 1;
end
end
end
wire baud_tick = (baud_counter == baud_limit);
// TX State Machine
always @(posedge clk or negedge rstn) begin
if (!rstn) begin
tx_state <= IDLE;
tx_bit_counter <= 0;
tx_line_reg <= 1'b1;
tx_active <= 1'b0;
tx_data_reg <= 8'h00;
end else if (baud_tick) begin
case (tx_state)
IDLE: begin
tx_line_reg <= 1'b1;
tx_active <= 1'b0;
if (tr_en && tx_data_w_en && tr_data_load) begin
tx_data_reg <= {tr_fifo_data_w, 1'b0}; // Load 7 bits + padding
tx_state <= START;
tx_active <= 1'b1;
tx_bit_counter <= 0;
end
end
START: begin
tx_line_reg <= 1'b0; // Start bit
tx_state <= DATA;
tx_bit_counter <= 0;
end
DATA: begin
tx_line_reg <= tx_data_reg[tx_bit_counter];
if (tx_bit_counter == 7) begin
tx_state <= STOP;
end else begin
tx_bit_counter <= tx_bit_counter + 1;
end
end
STOP: begin
tx_line_reg <= 1'b1; // Stop bit
tx_state <= IDLE;
tx_active <= 1'b0;
end
endcase
end
end
// RX State Machine
always @(posedge clk or negedge rstn) begin
if (!rstn) begin
rx_state <= IDLE;
rx_state_prev <= IDLE;
rx_bit_counter <= 0;
rx_data_reg <= 8'h00;
rx_active <= 1'b0;
rx_data_ready <= 1'b0;
end else begin
rx_state_prev <= rx_state;
if (baud_tick) begin
case (rx_state)
IDLE: begin
rx_active <= 1'b0;
if (!rx_data_in) begin // Start bit detected
rx_state <= START;
rx_bit_counter <= 0;
end
end
START: begin
if (!rx_data_in) begin // Confirm start bit
rx_state <= DATA;
rx_bit_counter <= 0;
rx_active <= 1'b1;
end else begin
rx_state <= IDLE; // False start
end
end
DATA: begin
rx_data_reg[rx_bit_counter] <= rx_data_in;
if (rx_bit_counter == 7) begin
rx_state <= STOP;
end else begin
rx_bit_counter <= rx_bit_counter + 1;
end
end
STOP: begin
if (rx_data_in) begin // Valid stop bit
rx_data_ready <= 1'b1;
end
rx_state <= IDLE;
rx_active <= 1'b0;
end
endcase
end
// Clear data ready flag when read
if (rx_data_read_en) begin
rx_data_ready <= 1'b0;
end
end
end
// Output assignments
assign tx_data_out = tx_line_reg;
assign rx_data_read_out = rx_data_reg;
assign transmit_busy = tx_active;
// Interrupt generation (simplified)
assign tx_i_interpt = !tx_active && tr_en; // TX ready
assign rx_i_interpt = rx_data_ready; // RX data available
assign tx_o_interpt = tx_active; // TX in progress
assign rx_o_interpt = rx_active; // RX in progress
endmodule
| module tt_um_uart (
input wire [7:0] ui_in, // control inputs
output wire [7:0] uo_out, // received data
input wire [7:0] uio_in, // tx_data (bits 7:1), rx_data (bit 0)
output wire [7:0] uio_out, // tx line + interrupt flags
output wire [7:0] uio_oe, // output enable
input wire ena, // always 1
input wire clk, // main clock
input wire rst_n // active low reset
);
// UART I/O wires
wire tx_line;
wire [7:0] rx_data;
wire tx_i_int, rx_i_int, tx_o_int, rx_o_int, tr_busy;
wire rx_we;
// Output assignments
assign uo_out = rx_data;
assign uio_out[0] = tx_line;
assign uio_out[1] = tx_i_int;
assign uio_out[2] = rx_i_int;
assign uio_out[3] = tx_o_int;
assign uio_out[4] = rx_o_int;
assign uio_out[5] = tr_busy;
assign uio_out[7:6] = 2'b00;
assign uio_oe = 8'b00111111; // uio_out[5:0] as outputs
// Instantiate top UART module
uart_top #(.WIDTH(8)) uart_inst (
.clk(clk),
.clk_sel(ui_in[2]),
.rstn(rst_n),
.tr_en(ui_in[0]),
.mode_osl(ui_in[1]),
.dlh_dll(16'h0020), // fixed baud rate for Tiny Tapeout
.tr_fifo_data_w(uio_in[7:1]),
.rx_data_in(uio_in[0]),
.tx_data_out(tx_line),
.rx_data_read_out(rx_data),
.rx_data_read_en(ui_in[5]),
.tx_data_w_en(ui_in[3]),
.transmit_busy(tr_busy),
.tx_i_interpt(tx_i_int),
.rx_i_interpt(rx_i_int),
.tx_o_interpt(tx_o_int),
.rx_o_interpt(rx_o_int),
.tr_data_load(ui_in[4])
);
endmodule |
ttsky25a-finale_1105 | ttsky25a-finale | tapeoutcutm-array_multiplier | task_array_mult8x8 | tt_um_mac_spst_tiny | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region. | /*
* MAC with SPST adder (TinyTapeout compliant)
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
// ============================================================
// Top-level TinyTapeout wrapper
// ============================================================
module tt_um_mac_spst_tiny (
input wire [7:0] ui_in, // Dedicated inputs: operand A
output wire [7:0] uo_out, // Dedicated outputs: accumulator low byte
input wire [7:0] uio_in, // IOs: input path (operand B / ext high byte in)
output wire [7:0] uio_out, // IOs: output path (accumulator high byte)
output wire [7:0] uio_oe, // IOs: enable path (1=drive output)
input wire ena, // always 1 when powered
input wire clk, // clock
input wire rst_n // reset, active low
);
// Internal signals
wire [7:0] out_low;
wire [7:0] out_high;
wire out_high_oe;
// Operand mapping
wire [7:0] operand_a = ui_in;
wire [7:0] operand_b = uio_in;
// Instantiate the MAC core
mac_spst_tiny dut (
.clk(clk),
.rst_n(rst_n),
.acc_en(ena),
.in_a(operand_a),
.in_b(operand_b),
.out_low(out_low),
.out_high(out_high),
.out_high_oe(out_high_oe)
);
// Outputs
assign uo_out = out_low; // low byte
assign uio_out = out_high; // high byte
assign uio_oe = {8{out_high_oe}}; // enable mask
endmodule
// ============================================================
// Core MAC with SPST Adder (no inout)
// ============================================================
module mac_spst_tiny (
input wire clk,
input wire rst_n,
input wire acc_en,
input wire [7:0] in_a,
input wire [7:0] in_b,
output wire [7:0] out_low,
output wire [7:0] out_high,
output wire out_high_oe
);
reg [15:0] acc;
wire [15:0] mult_out;
wire [15:0] sum;
// Multiplier
array_mult8x8 u_mult (
.a(in_a),
.b(in_b),
.y(mult_out)
);
// SPST Adder
spst_adder16 u_adder (
.a(acc),
.b(mult_out),
.sum(sum)
);
// Accumulator update
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
acc <= 16'd0;
end else if (acc_en) begin
acc <= sum;
end
end
// Outputs
assign out_low = acc[7:0];
assign out_high = acc[15:8];
assign out_high_oe = 1'b1; // always drive high byte
endmodule
// ============================================================
// 8x8 Array Multiplier
// ============================================================
module array_mult8x8 (
input wire [7:0] a,
input wire [7:0] b,
output wire [15:0] y
);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
// ============================================================
// 16-bit SPST Adder
// ============================================================
module spst_adder16 (
input wire [15:0] a,
input wire [15:0] b,
output wire [15:0] sum
);
assign sum = a + b; // Replace with SPST optimized logic if needed
endmodule
| module array_mult8x8 (
input wire [7:0] a,
input wire [7:0] b,
output wire [15:0] y
);
assign y = a * b;
endmodule |
ttsky25a-finale_1106 | ttsky25a-finale | tapeoutcutm-array_multiplier | task_mac_spst_tiny | tt_um_mac_spst_tiny | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region. | /*
* MAC with SPST adder (TinyTapeout compliant)
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
// ============================================================
// Top-level TinyTapeout wrapper
// ============================================================
module tt_um_mac_spst_tiny (
input wire [7:0] ui_in, // Dedicated inputs: operand A
output wire [7:0] uo_out, // Dedicated outputs: accumulator low byte
input wire [7:0] uio_in, // IOs: input path (operand B / ext high byte in)
output wire [7:0] uio_out, // IOs: output path (accumulator high byte)
output wire [7:0] uio_oe, // IOs: enable path (1=drive output)
input wire ena, // always 1 when powered
input wire clk, // clock
input wire rst_n // reset, active low
);
// Internal signals
wire [7:0] out_low;
wire [7:0] out_high;
wire out_high_oe;
// Operand mapping
wire [7:0] operand_a = ui_in;
wire [7:0] operand_b = uio_in;
// Instantiate the MAC core
mac_spst_tiny dut (
.clk(clk),
.rst_n(rst_n),
.acc_en(ena),
.in_a(operand_a),
.in_b(operand_b),
.out_low(out_low),
.out_high(out_high),
.out_high_oe(out_high_oe)
);
// Outputs
assign uo_out = out_low; // low byte
assign uio_out = out_high; // high byte
assign uio_oe = {8{out_high_oe}}; // enable mask
endmodule
// ============================================================
// Core MAC with SPST Adder (no inout)
// ============================================================
module mac_spst_tiny (
input wire clk,
input wire rst_n,
input wire acc_en,
input wire [7:0] in_a,
input wire [7:0] in_b,
output wire [7:0] out_low,
output wire [7:0] out_high,
output wire out_high_oe
);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
// ============================================================
// 8x8 Array Multiplier
// ============================================================
module array_mult8x8 (
input wire [7:0] a,
input wire [7:0] b,
output wire [15:0] y
);
assign y = a * b;
endmodule
// ============================================================
// 16-bit SPST Adder
// ============================================================
module spst_adder16 (
input wire [15:0] a,
input wire [15:0] b,
output wire [15:0] sum
);
assign sum = a + b; // Replace with SPST optimized logic if needed
endmodule
| module mac_spst_tiny (
input wire clk,
input wire rst_n,
input wire acc_en,
input wire [7:0] in_a,
input wire [7:0] in_b,
output wire [7:0] out_low,
output wire [7:0] out_high,
output wire out_high_oe
);
reg [15:0] acc;
wire [15:0] mult_out;
wire [15:0] sum;
// Multiplier
array_mult8x8 u_mult (
.a(in_a),
.b(in_b),
.y(mult_out)
);
// SPST Adder
spst_adder16 u_adder (
.a(acc),
.b(mult_out),
.sum(sum)
);
// Accumulator update
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
acc <= 16'd0;
end else if (acc_en) begin
acc <= sum;
end
end
// Outputs
assign out_low = acc[7:0];
assign out_high = acc[15:8];
assign out_high_oe = 1'b1; // always drive high byte
endmodule |
ttsky25a-finale_1107 | ttsky25a-finale | tapeoutcutm-array_multiplier | task_spst_adder16 | tt_um_mac_spst_tiny | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region. | /*
* MAC with SPST adder (TinyTapeout compliant)
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
// ============================================================
// Top-level TinyTapeout wrapper
// ============================================================
module tt_um_mac_spst_tiny (
input wire [7:0] ui_in, // Dedicated inputs: operand A
output wire [7:0] uo_out, // Dedicated outputs: accumulator low byte
input wire [7:0] uio_in, // IOs: input path (operand B / ext high byte in)
output wire [7:0] uio_out, // IOs: output path (accumulator high byte)
output wire [7:0] uio_oe, // IOs: enable path (1=drive output)
input wire ena, // always 1 when powered
input wire clk, // clock
input wire rst_n // reset, active low
);
// Internal signals
wire [7:0] out_low;
wire [7:0] out_high;
wire out_high_oe;
// Operand mapping
wire [7:0] operand_a = ui_in;
wire [7:0] operand_b = uio_in;
// Instantiate the MAC core
mac_spst_tiny dut (
.clk(clk),
.rst_n(rst_n),
.acc_en(ena),
.in_a(operand_a),
.in_b(operand_b),
.out_low(out_low),
.out_high(out_high),
.out_high_oe(out_high_oe)
);
// Outputs
assign uo_out = out_low; // low byte
assign uio_out = out_high; // high byte
assign uio_oe = {8{out_high_oe}}; // enable mask
endmodule
// ============================================================
// Core MAC with SPST Adder (no inout)
// ============================================================
module mac_spst_tiny (
input wire clk,
input wire rst_n,
input wire acc_en,
input wire [7:0] in_a,
input wire [7:0] in_b,
output wire [7:0] out_low,
output wire [7:0] out_high,
output wire out_high_oe
);
reg [15:0] acc;
wire [15:0] mult_out;
wire [15:0] sum;
// Multiplier
array_mult8x8 u_mult (
.a(in_a),
.b(in_b),
.y(mult_out)
);
// SPST Adder
spst_adder16 u_adder (
.a(acc),
.b(mult_out),
.sum(sum)
);
// Accumulator update
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
acc <= 16'd0;
end else if (acc_en) begin
acc <= sum;
end
end
// Outputs
assign out_low = acc[7:0];
assign out_high = acc[15:8];
assign out_high_oe = 1'b1; // always drive high byte
endmodule
// ============================================================
// 8x8 Array Multiplier
// ============================================================
module array_mult8x8 (
input wire [7:0] a,
input wire [7:0] b,
output wire [15:0] y
);
assign y = a * b;
endmodule
// ============================================================
// 16-bit SPST Adder
// ============================================================
module spst_adder16 (
input wire [15:0] a,
input wire [15:0] b,
output wire [15:0] sum
);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
| module spst_adder16 (
input wire [15:0] a,
input wire [15:0] b,
output wire [15:0] sum
);
assign sum = a + b; // Replace with SPST optimized logic if needed
endmodule |
ttsky25a-finale_1108 | ttsky25a-finale | tapeoutcutm-array_multiplier | task_tt_um_mac_spst_tiny | tt_um_mac_spst_tiny | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region. | /*
* MAC with SPST adder (TinyTapeout compliant)
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
// ============================================================
// Top-level TinyTapeout wrapper
// ============================================================
module tt_um_mac_spst_tiny (
input wire [7:0] ui_in, // Dedicated inputs: operand A
output wire [7:0] uo_out, // Dedicated outputs: accumulator low byte
input wire [7:0] uio_in, // IOs: input path (operand B / ext high byte in)
output wire [7:0] uio_out, // IOs: output path (accumulator high byte)
output wire [7:0] uio_oe, // IOs: enable path (1=drive output)
input wire ena, // always 1 when powered
input wire clk, // clock
input wire rst_n // reset, active low
);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
// ============================================================
// Core MAC with SPST Adder (no inout)
// ============================================================
module mac_spst_tiny (
input wire clk,
input wire rst_n,
input wire acc_en,
input wire [7:0] in_a,
input wire [7:0] in_b,
output wire [7:0] out_low,
output wire [7:0] out_high,
output wire out_high_oe
);
reg [15:0] acc;
wire [15:0] mult_out;
wire [15:0] sum;
// Multiplier
array_mult8x8 u_mult (
.a(in_a),
.b(in_b),
.y(mult_out)
);
// SPST Adder
spst_adder16 u_adder (
.a(acc),
.b(mult_out),
.sum(sum)
);
// Accumulator update
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
acc <= 16'd0;
end else if (acc_en) begin
acc <= sum;
end
end
// Outputs
assign out_low = acc[7:0];
assign out_high = acc[15:8];
assign out_high_oe = 1'b1; // always drive high byte
endmodule
// ============================================================
// 8x8 Array Multiplier
// ============================================================
module array_mult8x8 (
input wire [7:0] a,
input wire [7:0] b,
output wire [15:0] y
);
assign y = a * b;
endmodule
// ============================================================
// 16-bit SPST Adder
// ============================================================
module spst_adder16 (
input wire [15:0] a,
input wire [15:0] b,
output wire [15:0] sum
);
assign sum = a + b; // Replace with SPST optimized logic if needed
endmodule
| module tt_um_mac_spst_tiny (
input wire [7:0] ui_in, // Dedicated inputs: operand A
output wire [7:0] uo_out, // Dedicated outputs: accumulator low byte
input wire [7:0] uio_in, // IOs: input path (operand B / ext high byte in)
output wire [7:0] uio_out, // IOs: output path (accumulator high byte)
output wire [7:0] uio_oe, // IOs: enable path (1=drive output)
input wire ena, // always 1 when powered
input wire clk, // clock
input wire rst_n // reset, active low
);
// Internal signals
wire [7:0] out_low;
wire [7:0] out_high;
wire out_high_oe;
// Operand mapping
wire [7:0] operand_a = ui_in;
wire [7:0] operand_b = uio_in;
// Instantiate the MAC core
mac_spst_tiny dut (
.clk(clk),
.rst_n(rst_n),
.acc_en(ena),
.in_a(operand_a),
.in_b(operand_b),
.out_low(out_low),
.out_high(out_high),
.out_high_oe(out_high_oe)
);
// Outputs
assign uo_out = out_low; // low byte
assign uio_out = out_high; // high byte
assign uio_oe = {8{out_high_oe}}; // enable mask
endmodule |
ttsky25a-finale_1109 | ttsky25a-finale | tc503-ttsky25a-countdown-timer | task_clock_divider | tt_um_tc503_countdown_timer | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region. | /*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_tc503_countdown_timer (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // always 1 when the design is powered, so you can ignore it
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
wire rst = ! rst_n;
assign uio_oe = 8'b0000_0111;
assign uio_out[7:3] = 5'b0_0000;
countdown_timer countdown_timer (
.clk(clk),
.reset(rst),
.countdown0(ui_in[7]),
.enc0_a(ui_in[0]),
.enc0_b(ui_in[1]),
.enc1_a(ui_in[2]),
.enc1_b(ui_in[3]),
.enc2_a(ui_in[4]),
.enc2_b(ui_in[5]),
.pwm0_out(uio_out[0]),
.pwm1_out(uio_out[1]),
.pwm2_out(uio_out[2]),
.dis0_out(uo_out[6:0]),
.dis0_ctrl(uo_out[7])
);
// List all unused inputs to prevent warnings
wire _unused = &{ena, clk, rst_n, 1'b0};
endmodule
`default_nettype none
`timescale 1ns/1ns
module countdown_timer (
input clk,
input reset,
input countdown0,
input enc0_a,
input enc0_b,
input enc1_a,
input enc1_b,
input enc2_a,
input enc2_b,
output pwm0_out,
output pwm1_out,
output pwm2_out,
output reg [6:0] dis0_out,
output dis0_ctrl
);
wire enc0_a_db, enc0_b_db;
wire enc1_a_db, enc1_b_db;
wire enc2_a_db, enc2_b_db;
wire min_chk0;
wire [7:0] enc0, enc1, enc2;
reg [7:0] enc0_C, enc1_C, enc2_C;
reg [3:0] enc0_H, enc0_L;
/***
always @(*) begin
enc0_H <= enc0[7:4];
enc0_L <= enc0[3:0];
end
***/
always @(posedge clk) begin
if (reset) begin
enc0_C <= 0;
enc1_C <= 0;
enc2_C <= 0;
enc0_H <= 0;
enc0_L <= 0;
end else if (countdown0 == 1'b1) begin
if (min_chk0) begin
enc0_C <= enc0_C - 1;
enc0_H <= enc0_C[7:4];
enc0_L <= enc0_C[3:0];
end
end else begin
enc0_C <= enc0;
enc0_H <= enc0[7:4];
enc0_L <= enc0[3:0];
end
end
// debouncers, 2 for each encoder
debounce #(.HIST_LEN(8)) debounce0_a(.clk(clk), .reset(reset), .button(enc0_a), .debounced(enc0_a_db));
debounce #(.HIST_LEN(8)) debounce0_b(.clk(clk), .reset(reset), .button(enc0_b), .debounced(enc0_b_db));
debounce #(.HIST_LEN(8)) debounce1_a(.clk(clk), .reset(reset), .button(enc1_a), .debounced(enc1_a_db));
debounce #(.HIST_LEN(8)) debounce1_b(.clk(clk), .reset(reset), .button(enc1_b), .debounced(enc1_b_db));
debounce #(.HIST_LEN(8)) debounce2_a(.clk(clk), .reset(reset), .button(enc2_a), .debounced(enc2_a_db));
debounce #(.HIST_LEN(8)) debounce2_b(.clk(clk), .reset(reset), .button(enc2_b), .debounced(enc2_b_db));
// encoders
encoder #(.WIDTH(8)) encoder0(.clk(clk), .reset(reset), .a(enc0_a_db), .b(enc0_b_db), .value(enc0));
encoder #(.WIDTH(8)) encoder1(.clk(clk), .reset(reset), .a(enc1_a_db), .b(enc1_b_db), .value(enc1));
encoder #(.WIDTH(8)) encoder2(.clk(clk), .reset(reset), .a(enc2_a_db), .b(enc2_b_db), .value(enc2));
// pwm modules
pwm #(.WIDTH(8)) pwm0(.clk(clk), .reset(reset), .out(pwm0_out), .level(enc0));
pwm #(.WIDTH(8)) pwm1(.clk(clk), .reset(reset), .out(pwm1_out), .level(enc1));
pwm #(.WIDTH(8)) pwm2(.clk(clk), .reset(reset), .out(pwm2_out), .level(enc2));
// seven segment modules
seven_segment seven_segment0(.clk(clk), .reset(reset), .load(1'b1), .ten_count(enc0_H), .unit_count(enc0_L), .segments(dis0_out), .digit(dis0_ctrl));
// clock divider modules
clock_divider clock_divider0(.clk(clk), .reset(countdown0), .min_tick(min_chk0));
endmodule
`default_nettype none
`timescale 1ns/1ns
module debounce #(
parameter HIST_LEN = 8
)(
input wire clk,
input wire reset,
input wire button,
output reg debounced
);
localparam on_value = 2 ** HIST_LEN - 1;
reg [HIST_LEN-1:0] button_hist;
always @(posedge clk) begin
if(reset) begin
button_hist <= 0;
debounced <= 1'b0;
end else begin
button_hist <= {button_hist[HIST_LEN-2:0], button};
if(button_hist == on_value)
debounced <= 1'b1;
else if(button_hist == {HIST_LEN{1'b0}})
debounced <= 1'b0;
end
end
endmodule
`default_nettype none
`timescale 1ns/1ns
module encoder #(
parameter WIDTH = 8,
parameter INCREMENT = 1'b1
)(
input clk,
input reset,
input a,
input b,
output reg [WIDTH-1:0] value
);
reg old_a;
reg old_b;
always @(posedge clk) begin
if(reset) begin
old_a <= 0;
old_b <= 0;
value <= 0;
end else begin
// last values
old_a <= a;
old_b <= b;
// state machine
case ({a,old_a,b,old_b})
4'b1000: value <= value + INCREMENT;
4'b0111: value <= value + INCREMENT;
4'b0010: value <= value - INCREMENT;
4'b1101: value <= value - INCREMENT;
default: value <= value;
endcase
end
end
endmodule
`default_nettype none
`timescale 1ns/1ns
module pwm #(
parameter WIDTH = 8,
parameter INVERT = 0
) (
input wire clk,
input wire reset,
output reg out,
input wire [WIDTH-1:0] level
);
reg [WIDTH-1:0] count;
wire pwm_on = count < level;
always @(posedge clk) begin
if(reset)
count <= 1'b0;
else
count <= count + 1'b1;
end
always @(posedge clk) begin
if(reset)
out <= 0;
else
out <= INVERT == 1'b0 ? pwm_on : ! pwm_on;
end
endmodule
`default_nettype none
`timescale 1ns/1ps
module seven_segment (
input wire clk,
input wire reset,
input wire load,
input wire [3:0] ten_count,
input wire [3:0] unit_count,
output reg [6:0] segments,
output reg digit
);
reg [3:0] ten_count_reg;
reg [3:0] unit_count_reg;
wire [3:0] decode;
always @(posedge clk) begin
if (reset) begin
ten_count_reg <= 0;
unit_count_reg <=0;
digit <=0;
end else
digit <= !digit;
if (load) begin
ten_count_reg <= ten_count;
unit_count_reg <= unit_count;
end
end
assign decode = digit ? ten_count_reg : unit_count_reg;
always @(*) begin
case(decode)
// 7654321
0: segments = 7'b0111111;
1: segments = 7'b0000110;
2: segments = 7'b1011011;
3: segments = 7'b1001111;
4: segments = 7'b1100110;
5: segments = 7'b1101101;
6: segments = 7'b1111100;
7: segments = 7'b0000111;
8: segments = 7'b1111111;
9: segments = 7'b1100111;
default:
segments = 7'b0000000;
endcase
end
endmodule
`default_nettype none
`timescale 1ns/1ps
module clock_divider (
input clk,
input reset,
output reg min_tick
);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
| module clock_divider (
input clk,
input reset,
output reg min_tick
);
// Adjust max_count for a 1-minute period based on your system clock frequency
// localparam MAX_COUNT = 960000000; // (clock_frequency * 60) - 1
// localparam BITS = 30;
// reg [BITS-1:0] counter; // BITS depends on MAX_COUNT
reg [30-1:0] counter; // BITS depends on MAX_COUNT
always @(posedge clk or posedge reset) begin
if (reset) begin
counter <= 0;
min_tick <= 0;
end else if (counter == 960000000) begin
counter <= 0;
min_tick <= 1'b1;
end else begin
counter <= counter + 1;
min_tick <= 1'b0;
end
end
endmodule |
ttsky25a-finale_1110 | ttsky25a-finale | tc503-ttsky25a-countdown-timer | task_countdown_timer | tt_um_tc503_countdown_timer | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region. | /*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_tc503_countdown_timer (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // always 1 when the design is powered, so you can ignore it
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
wire rst = ! rst_n;
assign uio_oe = 8'b0000_0111;
assign uio_out[7:3] = 5'b0_0000;
countdown_timer countdown_timer (
.clk(clk),
.reset(rst),
.countdown0(ui_in[7]),
.enc0_a(ui_in[0]),
.enc0_b(ui_in[1]),
.enc1_a(ui_in[2]),
.enc1_b(ui_in[3]),
.enc2_a(ui_in[4]),
.enc2_b(ui_in[5]),
.pwm0_out(uio_out[0]),
.pwm1_out(uio_out[1]),
.pwm2_out(uio_out[2]),
.dis0_out(uo_out[6:0]),
.dis0_ctrl(uo_out[7])
);
// List all unused inputs to prevent warnings
wire _unused = &{ena, clk, rst_n, 1'b0};
endmodule
`default_nettype none
`timescale 1ns/1ns
module countdown_timer (
input clk,
input reset,
input countdown0,
input enc0_a,
input enc0_b,
input enc1_a,
input enc1_b,
input enc2_a,
input enc2_b,
output pwm0_out,
output pwm1_out,
output pwm2_out,
output reg [6:0] dis0_out,
output dis0_ctrl
);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
`default_nettype none
`timescale 1ns/1ns
module debounce #(
parameter HIST_LEN = 8
)(
input wire clk,
input wire reset,
input wire button,
output reg debounced
);
localparam on_value = 2 ** HIST_LEN - 1;
reg [HIST_LEN-1:0] button_hist;
always @(posedge clk) begin
if(reset) begin
button_hist <= 0;
debounced <= 1'b0;
end else begin
button_hist <= {button_hist[HIST_LEN-2:0], button};
if(button_hist == on_value)
debounced <= 1'b1;
else if(button_hist == {HIST_LEN{1'b0}})
debounced <= 1'b0;
end
end
endmodule
`default_nettype none
`timescale 1ns/1ns
module encoder #(
parameter WIDTH = 8,
parameter INCREMENT = 1'b1
)(
input clk,
input reset,
input a,
input b,
output reg [WIDTH-1:0] value
);
reg old_a;
reg old_b;
always @(posedge clk) begin
if(reset) begin
old_a <= 0;
old_b <= 0;
value <= 0;
end else begin
// last values
old_a <= a;
old_b <= b;
// state machine
case ({a,old_a,b,old_b})
4'b1000: value <= value + INCREMENT;
4'b0111: value <= value + INCREMENT;
4'b0010: value <= value - INCREMENT;
4'b1101: value <= value - INCREMENT;
default: value <= value;
endcase
end
end
endmodule
`default_nettype none
`timescale 1ns/1ns
module pwm #(
parameter WIDTH = 8,
parameter INVERT = 0
) (
input wire clk,
input wire reset,
output reg out,
input wire [WIDTH-1:0] level
);
reg [WIDTH-1:0] count;
wire pwm_on = count < level;
always @(posedge clk) begin
if(reset)
count <= 1'b0;
else
count <= count + 1'b1;
end
always @(posedge clk) begin
if(reset)
out <= 0;
else
out <= INVERT == 1'b0 ? pwm_on : ! pwm_on;
end
endmodule
`default_nettype none
`timescale 1ns/1ps
module seven_segment (
input wire clk,
input wire reset,
input wire load,
input wire [3:0] ten_count,
input wire [3:0] unit_count,
output reg [6:0] segments,
output reg digit
);
reg [3:0] ten_count_reg;
reg [3:0] unit_count_reg;
wire [3:0] decode;
always @(posedge clk) begin
if (reset) begin
ten_count_reg <= 0;
unit_count_reg <=0;
digit <=0;
end else
digit <= !digit;
if (load) begin
ten_count_reg <= ten_count;
unit_count_reg <= unit_count;
end
end
assign decode = digit ? ten_count_reg : unit_count_reg;
always @(*) begin
case(decode)
// 7654321
0: segments = 7'b0111111;
1: segments = 7'b0000110;
2: segments = 7'b1011011;
3: segments = 7'b1001111;
4: segments = 7'b1100110;
5: segments = 7'b1101101;
6: segments = 7'b1111100;
7: segments = 7'b0000111;
8: segments = 7'b1111111;
9: segments = 7'b1100111;
default:
segments = 7'b0000000;
endcase
end
endmodule
`default_nettype none
`timescale 1ns/1ps
module clock_divider (
input clk,
input reset,
output reg min_tick
);
// Adjust max_count for a 1-minute period based on your system clock frequency
// localparam MAX_COUNT = 960000000; // (clock_frequency * 60) - 1
// localparam BITS = 30;
// reg [BITS-1:0] counter; // BITS depends on MAX_COUNT
reg [30-1:0] counter; // BITS depends on MAX_COUNT
always @(posedge clk or posedge reset) begin
if (reset) begin
counter <= 0;
min_tick <= 0;
end else if (counter == 960000000) begin
counter <= 0;
min_tick <= 1'b1;
end else begin
counter <= counter + 1;
min_tick <= 1'b0;
end
end
endmodule
| module countdown_timer (
input clk,
input reset,
input countdown0,
input enc0_a,
input enc0_b,
input enc1_a,
input enc1_b,
input enc2_a,
input enc2_b,
output pwm0_out,
output pwm1_out,
output pwm2_out,
output reg [6:0] dis0_out,
output dis0_ctrl
);
wire enc0_a_db, enc0_b_db;
wire enc1_a_db, enc1_b_db;
wire enc2_a_db, enc2_b_db;
wire min_chk0;
wire [7:0] enc0, enc1, enc2;
reg [7:0] enc0_C, enc1_C, enc2_C;
reg [3:0] enc0_H, enc0_L;
/***
always @(*) begin
enc0_H <= enc0[7:4];
enc0_L <= enc0[3:0];
end
***/
always @(posedge clk) begin
if (reset) begin
enc0_C <= 0;
enc1_C <= 0;
enc2_C <= 0;
enc0_H <= 0;
enc0_L <= 0;
end else if (countdown0 == 1'b1) begin
if (min_chk0) begin
enc0_C <= enc0_C - 1;
enc0_H <= enc0_C[7:4];
enc0_L <= enc0_C[3:0];
end
end else begin
enc0_C <= enc0;
enc0_H <= enc0[7:4];
enc0_L <= enc0[3:0];
end
end
// debouncers, 2 for each encoder
debounce #(.HIST_LEN(8)) debounce0_a(.clk(clk), .reset(reset), .button(enc0_a), .debounced(enc0_a_db));
debounce #(.HIST_LEN(8)) debounce0_b(.clk(clk), .reset(reset), .button(enc0_b), .debounced(enc0_b_db));
debounce #(.HIST_LEN(8)) debounce1_a(.clk(clk), .reset(reset), .button(enc1_a), .debounced(enc1_a_db));
debounce #(.HIST_LEN(8)) debounce1_b(.clk(clk), .reset(reset), .button(enc1_b), .debounced(enc1_b_db));
debounce #(.HIST_LEN(8)) debounce2_a(.clk(clk), .reset(reset), .button(enc2_a), .debounced(enc2_a_db));
debounce #(.HIST_LEN(8)) debounce2_b(.clk(clk), .reset(reset), .button(enc2_b), .debounced(enc2_b_db));
// encoders
encoder #(.WIDTH(8)) encoder0(.clk(clk), .reset(reset), .a(enc0_a_db), .b(enc0_b_db), .value(enc0));
encoder #(.WIDTH(8)) encoder1(.clk(clk), .reset(reset), .a(enc1_a_db), .b(enc1_b_db), .value(enc1));
encoder #(.WIDTH(8)) encoder2(.clk(clk), .reset(reset), .a(enc2_a_db), .b(enc2_b_db), .value(enc2));
// pwm modules
pwm #(.WIDTH(8)) pwm0(.clk(clk), .reset(reset), .out(pwm0_out), .level(enc0));
pwm #(.WIDTH(8)) pwm1(.clk(clk), .reset(reset), .out(pwm1_out), .level(enc1));
pwm #(.WIDTH(8)) pwm2(.clk(clk), .reset(reset), .out(pwm2_out), .level(enc2));
// seven segment modules
seven_segment seven_segment0(.clk(clk), .reset(reset), .load(1'b1), .ten_count(enc0_H), .unit_count(enc0_L), .segments(dis0_out), .digit(dis0_ctrl));
// clock divider modules
clock_divider clock_divider0(.clk(clk), .reset(countdown0), .min_tick(min_chk0));
endmodule |
ttsky25a-finale_1111 | ttsky25a-finale | tc503-ttsky25a-countdown-timer | task_seven_segment | tt_um_tc503_countdown_timer | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region. | /*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_tc503_countdown_timer (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // always 1 when the design is powered, so you can ignore it
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
wire rst = ! rst_n;
assign uio_oe = 8'b0000_0111;
assign uio_out[7:3] = 5'b0_0000;
countdown_timer countdown_timer (
.clk(clk),
.reset(rst),
.countdown0(ui_in[7]),
.enc0_a(ui_in[0]),
.enc0_b(ui_in[1]),
.enc1_a(ui_in[2]),
.enc1_b(ui_in[3]),
.enc2_a(ui_in[4]),
.enc2_b(ui_in[5]),
.pwm0_out(uio_out[0]),
.pwm1_out(uio_out[1]),
.pwm2_out(uio_out[2]),
.dis0_out(uo_out[6:0]),
.dis0_ctrl(uo_out[7])
);
// List all unused inputs to prevent warnings
wire _unused = &{ena, clk, rst_n, 1'b0};
endmodule
`default_nettype none
`timescale 1ns/1ns
module countdown_timer (
input clk,
input reset,
input countdown0,
input enc0_a,
input enc0_b,
input enc1_a,
input enc1_b,
input enc2_a,
input enc2_b,
output pwm0_out,
output pwm1_out,
output pwm2_out,
output reg [6:0] dis0_out,
output dis0_ctrl
);
wire enc0_a_db, enc0_b_db;
wire enc1_a_db, enc1_b_db;
wire enc2_a_db, enc2_b_db;
wire min_chk0;
wire [7:0] enc0, enc1, enc2;
reg [7:0] enc0_C, enc1_C, enc2_C;
reg [3:0] enc0_H, enc0_L;
/***
always @(*) begin
enc0_H <= enc0[7:4];
enc0_L <= enc0[3:0];
end
***/
always @(posedge clk) begin
if (reset) begin
enc0_C <= 0;
enc1_C <= 0;
enc2_C <= 0;
enc0_H <= 0;
enc0_L <= 0;
end else if (countdown0 == 1'b1) begin
if (min_chk0) begin
enc0_C <= enc0_C - 1;
enc0_H <= enc0_C[7:4];
enc0_L <= enc0_C[3:0];
end
end else begin
enc0_C <= enc0;
enc0_H <= enc0[7:4];
enc0_L <= enc0[3:0];
end
end
// debouncers, 2 for each encoder
debounce #(.HIST_LEN(8)) debounce0_a(.clk(clk), .reset(reset), .button(enc0_a), .debounced(enc0_a_db));
debounce #(.HIST_LEN(8)) debounce0_b(.clk(clk), .reset(reset), .button(enc0_b), .debounced(enc0_b_db));
debounce #(.HIST_LEN(8)) debounce1_a(.clk(clk), .reset(reset), .button(enc1_a), .debounced(enc1_a_db));
debounce #(.HIST_LEN(8)) debounce1_b(.clk(clk), .reset(reset), .button(enc1_b), .debounced(enc1_b_db));
debounce #(.HIST_LEN(8)) debounce2_a(.clk(clk), .reset(reset), .button(enc2_a), .debounced(enc2_a_db));
debounce #(.HIST_LEN(8)) debounce2_b(.clk(clk), .reset(reset), .button(enc2_b), .debounced(enc2_b_db));
// encoders
encoder #(.WIDTH(8)) encoder0(.clk(clk), .reset(reset), .a(enc0_a_db), .b(enc0_b_db), .value(enc0));
encoder #(.WIDTH(8)) encoder1(.clk(clk), .reset(reset), .a(enc1_a_db), .b(enc1_b_db), .value(enc1));
encoder #(.WIDTH(8)) encoder2(.clk(clk), .reset(reset), .a(enc2_a_db), .b(enc2_b_db), .value(enc2));
// pwm modules
pwm #(.WIDTH(8)) pwm0(.clk(clk), .reset(reset), .out(pwm0_out), .level(enc0));
pwm #(.WIDTH(8)) pwm1(.clk(clk), .reset(reset), .out(pwm1_out), .level(enc1));
pwm #(.WIDTH(8)) pwm2(.clk(clk), .reset(reset), .out(pwm2_out), .level(enc2));
// seven segment modules
seven_segment seven_segment0(.clk(clk), .reset(reset), .load(1'b1), .ten_count(enc0_H), .unit_count(enc0_L), .segments(dis0_out), .digit(dis0_ctrl));
// clock divider modules
clock_divider clock_divider0(.clk(clk), .reset(countdown0), .min_tick(min_chk0));
endmodule
`default_nettype none
`timescale 1ns/1ns
module debounce #(
parameter HIST_LEN = 8
)(
input wire clk,
input wire reset,
input wire button,
output reg debounced
);
localparam on_value = 2 ** HIST_LEN - 1;
reg [HIST_LEN-1:0] button_hist;
always @(posedge clk) begin
if(reset) begin
button_hist <= 0;
debounced <= 1'b0;
end else begin
button_hist <= {button_hist[HIST_LEN-2:0], button};
if(button_hist == on_value)
debounced <= 1'b1;
else if(button_hist == {HIST_LEN{1'b0}})
debounced <= 1'b0;
end
end
endmodule
`default_nettype none
`timescale 1ns/1ns
module encoder #(
parameter WIDTH = 8,
parameter INCREMENT = 1'b1
)(
input clk,
input reset,
input a,
input b,
output reg [WIDTH-1:0] value
);
reg old_a;
reg old_b;
always @(posedge clk) begin
if(reset) begin
old_a <= 0;
old_b <= 0;
value <= 0;
end else begin
// last values
old_a <= a;
old_b <= b;
// state machine
case ({a,old_a,b,old_b})
4'b1000: value <= value + INCREMENT;
4'b0111: value <= value + INCREMENT;
4'b0010: value <= value - INCREMENT;
4'b1101: value <= value - INCREMENT;
default: value <= value;
endcase
end
end
endmodule
`default_nettype none
`timescale 1ns/1ns
module pwm #(
parameter WIDTH = 8,
parameter INVERT = 0
) (
input wire clk,
input wire reset,
output reg out,
input wire [WIDTH-1:0] level
);
reg [WIDTH-1:0] count;
wire pwm_on = count < level;
always @(posedge clk) begin
if(reset)
count <= 1'b0;
else
count <= count + 1'b1;
end
always @(posedge clk) begin
if(reset)
out <= 0;
else
out <= INVERT == 1'b0 ? pwm_on : ! pwm_on;
end
endmodule
`default_nettype none
`timescale 1ns/1ps
module seven_segment (
input wire clk,
input wire reset,
input wire load,
input wire [3:0] ten_count,
input wire [3:0] unit_count,
output reg [6:0] segments,
output reg digit
);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
`default_nettype none
`timescale 1ns/1ps
module clock_divider (
input clk,
input reset,
output reg min_tick
);
// Adjust max_count for a 1-minute period based on your system clock frequency
// localparam MAX_COUNT = 960000000; // (clock_frequency * 60) - 1
// localparam BITS = 30;
// reg [BITS-1:0] counter; // BITS depends on MAX_COUNT
reg [30-1:0] counter; // BITS depends on MAX_COUNT
always @(posedge clk or posedge reset) begin
if (reset) begin
counter <= 0;
min_tick <= 0;
end else if (counter == 960000000) begin
counter <= 0;
min_tick <= 1'b1;
end else begin
counter <= counter + 1;
min_tick <= 1'b0;
end
end
endmodule
| module seven_segment (
input wire clk,
input wire reset,
input wire load,
input wire [3:0] ten_count,
input wire [3:0] unit_count,
output reg [6:0] segments,
output reg digit
);
reg [3:0] ten_count_reg;
reg [3:0] unit_count_reg;
wire [3:0] decode;
always @(posedge clk) begin
if (reset) begin
ten_count_reg <= 0;
unit_count_reg <=0;
digit <=0;
end else
digit <= !digit;
if (load) begin
ten_count_reg <= ten_count;
unit_count_reg <= unit_count;
end
end
assign decode = digit ? ten_count_reg : unit_count_reg;
always @(*) begin
case(decode)
// 7654321
0: segments = 7'b0111111;
1: segments = 7'b0000110;
2: segments = 7'b1011011;
3: segments = 7'b1001111;
4: segments = 7'b1100110;
5: segments = 7'b1101101;
6: segments = 7'b1111100;
7: segments = 7'b0000111;
8: segments = 7'b1111111;
9: segments = 7'b1100111;
default:
segments = 7'b0000000;
endcase
end
endmodule |
ttsky25a-finale_1112 | ttsky25a-finale | tc503-ttsky25a-countdown-timer | task_tt_um_tc503_countdown_timer | tt_um_tc503_countdown_timer | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region. | /*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_tc503_countdown_timer (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // always 1 when the design is powered, so you can ignore it
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
`default_nettype none
`timescale 1ns/1ns
module countdown_timer (
input clk,
input reset,
input countdown0,
input enc0_a,
input enc0_b,
input enc1_a,
input enc1_b,
input enc2_a,
input enc2_b,
output pwm0_out,
output pwm1_out,
output pwm2_out,
output reg [6:0] dis0_out,
output dis0_ctrl
);
wire enc0_a_db, enc0_b_db;
wire enc1_a_db, enc1_b_db;
wire enc2_a_db, enc2_b_db;
wire min_chk0;
wire [7:0] enc0, enc1, enc2;
reg [7:0] enc0_C, enc1_C, enc2_C;
reg [3:0] enc0_H, enc0_L;
/***
always @(*) begin
enc0_H <= enc0[7:4];
enc0_L <= enc0[3:0];
end
***/
always @(posedge clk) begin
if (reset) begin
enc0_C <= 0;
enc1_C <= 0;
enc2_C <= 0;
enc0_H <= 0;
enc0_L <= 0;
end else if (countdown0 == 1'b1) begin
if (min_chk0) begin
enc0_C <= enc0_C - 1;
enc0_H <= enc0_C[7:4];
enc0_L <= enc0_C[3:0];
end
end else begin
enc0_C <= enc0;
enc0_H <= enc0[7:4];
enc0_L <= enc0[3:0];
end
end
// debouncers, 2 for each encoder
debounce #(.HIST_LEN(8)) debounce0_a(.clk(clk), .reset(reset), .button(enc0_a), .debounced(enc0_a_db));
debounce #(.HIST_LEN(8)) debounce0_b(.clk(clk), .reset(reset), .button(enc0_b), .debounced(enc0_b_db));
debounce #(.HIST_LEN(8)) debounce1_a(.clk(clk), .reset(reset), .button(enc1_a), .debounced(enc1_a_db));
debounce #(.HIST_LEN(8)) debounce1_b(.clk(clk), .reset(reset), .button(enc1_b), .debounced(enc1_b_db));
debounce #(.HIST_LEN(8)) debounce2_a(.clk(clk), .reset(reset), .button(enc2_a), .debounced(enc2_a_db));
debounce #(.HIST_LEN(8)) debounce2_b(.clk(clk), .reset(reset), .button(enc2_b), .debounced(enc2_b_db));
// encoders
encoder #(.WIDTH(8)) encoder0(.clk(clk), .reset(reset), .a(enc0_a_db), .b(enc0_b_db), .value(enc0));
encoder #(.WIDTH(8)) encoder1(.clk(clk), .reset(reset), .a(enc1_a_db), .b(enc1_b_db), .value(enc1));
encoder #(.WIDTH(8)) encoder2(.clk(clk), .reset(reset), .a(enc2_a_db), .b(enc2_b_db), .value(enc2));
// pwm modules
pwm #(.WIDTH(8)) pwm0(.clk(clk), .reset(reset), .out(pwm0_out), .level(enc0));
pwm #(.WIDTH(8)) pwm1(.clk(clk), .reset(reset), .out(pwm1_out), .level(enc1));
pwm #(.WIDTH(8)) pwm2(.clk(clk), .reset(reset), .out(pwm2_out), .level(enc2));
// seven segment modules
seven_segment seven_segment0(.clk(clk), .reset(reset), .load(1'b1), .ten_count(enc0_H), .unit_count(enc0_L), .segments(dis0_out), .digit(dis0_ctrl));
// clock divider modules
clock_divider clock_divider0(.clk(clk), .reset(countdown0), .min_tick(min_chk0));
endmodule
`default_nettype none
`timescale 1ns/1ns
module debounce #(
parameter HIST_LEN = 8
)(
input wire clk,
input wire reset,
input wire button,
output reg debounced
);
localparam on_value = 2 ** HIST_LEN - 1;
reg [HIST_LEN-1:0] button_hist;
always @(posedge clk) begin
if(reset) begin
button_hist <= 0;
debounced <= 1'b0;
end else begin
button_hist <= {button_hist[HIST_LEN-2:0], button};
if(button_hist == on_value)
debounced <= 1'b1;
else if(button_hist == {HIST_LEN{1'b0}})
debounced <= 1'b0;
end
end
endmodule
`default_nettype none
`timescale 1ns/1ns
module encoder #(
parameter WIDTH = 8,
parameter INCREMENT = 1'b1
)(
input clk,
input reset,
input a,
input b,
output reg [WIDTH-1:0] value
);
reg old_a;
reg old_b;
always @(posedge clk) begin
if(reset) begin
old_a <= 0;
old_b <= 0;
value <= 0;
end else begin
// last values
old_a <= a;
old_b <= b;
// state machine
case ({a,old_a,b,old_b})
4'b1000: value <= value + INCREMENT;
4'b0111: value <= value + INCREMENT;
4'b0010: value <= value - INCREMENT;
4'b1101: value <= value - INCREMENT;
default: value <= value;
endcase
end
end
endmodule
`default_nettype none
`timescale 1ns/1ns
module pwm #(
parameter WIDTH = 8,
parameter INVERT = 0
) (
input wire clk,
input wire reset,
output reg out,
input wire [WIDTH-1:0] level
);
reg [WIDTH-1:0] count;
wire pwm_on = count < level;
always @(posedge clk) begin
if(reset)
count <= 1'b0;
else
count <= count + 1'b1;
end
always @(posedge clk) begin
if(reset)
out <= 0;
else
out <= INVERT == 1'b0 ? pwm_on : ! pwm_on;
end
endmodule
`default_nettype none
`timescale 1ns/1ps
module seven_segment (
input wire clk,
input wire reset,
input wire load,
input wire [3:0] ten_count,
input wire [3:0] unit_count,
output reg [6:0] segments,
output reg digit
);
reg [3:0] ten_count_reg;
reg [3:0] unit_count_reg;
wire [3:0] decode;
always @(posedge clk) begin
if (reset) begin
ten_count_reg <= 0;
unit_count_reg <=0;
digit <=0;
end else
digit <= !digit;
if (load) begin
ten_count_reg <= ten_count;
unit_count_reg <= unit_count;
end
end
assign decode = digit ? ten_count_reg : unit_count_reg;
always @(*) begin
case(decode)
// 7654321
0: segments = 7'b0111111;
1: segments = 7'b0000110;
2: segments = 7'b1011011;
3: segments = 7'b1001111;
4: segments = 7'b1100110;
5: segments = 7'b1101101;
6: segments = 7'b1111100;
7: segments = 7'b0000111;
8: segments = 7'b1111111;
9: segments = 7'b1100111;
default:
segments = 7'b0000000;
endcase
end
endmodule
`default_nettype none
`timescale 1ns/1ps
module clock_divider (
input clk,
input reset,
output reg min_tick
);
// Adjust max_count for a 1-minute period based on your system clock frequency
// localparam MAX_COUNT = 960000000; // (clock_frequency * 60) - 1
// localparam BITS = 30;
// reg [BITS-1:0] counter; // BITS depends on MAX_COUNT
reg [30-1:0] counter; // BITS depends on MAX_COUNT
always @(posedge clk or posedge reset) begin
if (reset) begin
counter <= 0;
min_tick <= 0;
end else if (counter == 960000000) begin
counter <= 0;
min_tick <= 1'b1;
end else begin
counter <= counter + 1;
min_tick <= 1'b0;
end
end
endmodule
| module tt_um_tc503_countdown_timer (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // always 1 when the design is powered, so you can ignore it
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
wire rst = ! rst_n;
assign uio_oe = 8'b0000_0111;
assign uio_out[7:3] = 5'b0_0000;
countdown_timer countdown_timer (
.clk(clk),
.reset(rst),
.countdown0(ui_in[7]),
.enc0_a(ui_in[0]),
.enc0_b(ui_in[1]),
.enc1_a(ui_in[2]),
.enc1_b(ui_in[3]),
.enc2_a(ui_in[4]),
.enc2_b(ui_in[5]),
.pwm0_out(uio_out[0]),
.pwm1_out(uio_out[1]),
.pwm2_out(uio_out[2]),
.dis0_out(uo_out[6:0]),
.dis0_ctrl(uo_out[7])
);
// List all unused inputs to prevent warnings
wire _unused = &{ena, clk, rst_n, 1'b0};
endmodule |
ttsky25a-finale_1113 | ttsky25a-finale | tgrillz-tt_um_sixSidedDie | task_sevenSeg | tt_um_tgrillz_sixSidedDie | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region. | /*
* Copyright (c) 2025 tgrillz
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_tgrillz_sixSidedDie #(parameter STATE = 8'b1000_0001)(
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // ^ this is enables this IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // always 1 when the design is powered, so you can ignore it
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
// All output pins must be assigned. If not used, assign to 0.
// assign uo_out = ui_in + uio_in; // Example: ou_out is the sum of ui_in and uio_in
assign uio_out = 0;
assign uio_oe = 0;
assign uo_out[7] = 1'b0;
// List all unused inputs to prevent warnings
// wire _unused = &{ena, clk, rst_n, 1'b0};
wire _unused = &{ena, uio_in, ui_in[7:1], 1'b0};
reg [7:0] roll;
reg [7:0] thisRoll;
reg [7:0] outRoll;
reg lastReset;
reg [6:0] outNum;
// Creats a "randomly" generated number using lfsr
// Note this will always turn on to 0 if the dip switch is set to on at start up
// A reset or a reset of the dipswitch is needed to adjust
// Assumes an explicit reset at initilization
eightBitlfsr lfsr(.clk(clk), .rst_n(rst_n), .seed(STATE), .out(thisRoll));
always @(posedge clk) begin
if (!rst_n) begin
roll <= 8'b0000_0000;
outRoll <= 8'b0000_0000;
lastReset <= 1'b1;
end else begin
// if "on"
if (ui_in[0]) begin
// if new roll after reset get new number
if (!lastReset) begin
roll <= thisRoll;
// otherwise hold number until next roll
end else begin
roll <= roll;
end
// if "off" keep cycling through numbers
end else begin
roll <= thisRoll;
end
// update tracker of last reset value
if (outNum == 7'b0000000)
lastReset <= 1'b0;
else
lastReset <= rst_n;
end
// Outputs 0 if in "off" state
if (ui_in[0]) begin
outRoll <= roll;
end else begin
outRoll <= 0;
end
end
// Output number to 7 segment display
sevenSeg sevenSegment(.clk(clk), .rst_n(rst_n), .inputNum(outRoll), .out(outNum));
// Assign 7 segment bits to LSB of outwire
assign uo_out[6:0] = outNum;
endmodule
`default_nettype none
module eightBitlfsr # (parameter BITNUM = 8)(
input wire clk,
input wire rst_n,
input wire [7:0] seed,
output wire [7:0] out
);
reg [BITNUM-1:0] state = 8'b1000_0001;
reg [7:0] lfsrVal;
reg [7:0] insideRoll;
always @(posedge clk) begin
if(!rst_n) begin
state <= seed;
end else begin
state <= seed;
if (state == 8'b0000_0000) begin
state <= 8'b1000_0001;
end else begin
// Create a "randomly" generated number using lfsr
state <= {state[6:0], (state[0] ^ state[3] ^ state[7])};
end
lfsrVal <= {5'b00000, state[2:0]}; // isolates 3 LSB
if (lfsrVal < 6) begin
insideRoll <= lfsrVal + 1; // number between 1 and 6
end else begin
insideRoll <= insideRoll; // hold until next valid number
end
end
end
assign out = insideRoll;
endmodule
`default_nettype none
module sevenSeg (
input wire clk,
input wire rst_n,
input wire [7:0] inputNum,
output wire [6:0] out
);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
| module sevenSeg (
input wire clk,
input wire rst_n,
input wire [7:0] inputNum,
output wire [6:0] out
);
reg [7:0] displayIt;
reg [6:0] outNum;
always @(posedge clk) begin
if (!rst_n) begin
displayIt <= 0;
end else begin
displayIt <= inputNum;
end
end
always @(*) begin
// Output number to 7 segment display
case(displayIt)
0: outNum = 7'b0111111;
1: outNum = 7'b0000110;
2: outNum = 7'b1011011;
3: outNum = 7'b1001111;
4: outNum = 7'b1100110;
5: outNum = 7'b1101101;
6: outNum = 7'b1111100;
7: outNum = 7'b0000111;
8: outNum = 7'b1111111;
9: outNum = 7'b1100111;
default:
outNum = 7'b0000000;
endcase
end
assign out = outNum;
endmodule |
ttsky25a-finale_1114 | ttsky25a-finale | vagesh007-CF-2024-TT12-11 | task_clk_div | tt_um_fifo | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region. | module tt_um_fifo #(parameter DSIZE=8, parameter ASIZE=4)
(
input wire [7:0] ui_in,
output wire [7:0] uo_out,
input wire [7:0] uio_in,
output wire [7:0] uio_out,
output wire [7:0] uio_oe,
input wire ena,
input wire clk,
input wire rst_n
);
assign uo_out = rdata;
wire [DSIZE-1:0] rdata;
wire wfull, rempty;
assign uio_oe = 8'b00100111;
assign uio_out[0] = rempty;
assign uio_out[1] = wfull;
wire [DSIZE-1:0] wdata = ui_in;
wire winc = uio_in[7];
wire rinc = uio_in[6];
wire rrst_n = uio_in[3];
wire wrst_n = uio_in[4];
assign uio_out[7:6] = 0;
assign uio_out[4:3] = 0;
assign uio_out[5] = wclk;
assign uio_out[2] = rclk;
// Internal divided clocks
wire wclk, rclk;
// Clock divider instance
clk_div clk_div_inst (
.clk (clk),
.r_rst (rrst_n), // active-high reset for divider
.w_rst (wrst_n),
.wclk (wclk),
.rclk (rclk)
);
// Address & pointers
wire [ASIZE-1:0] waddr, raddr;
wire [ASIZE:0] rptr, wptr, WSR2_ptr, RSW2_ptr;
wire wclken = (winc && !wfull);
wire rclken = (rinc && !rempty);
// Synchronizers
sync_R2W sync_r2w (
.RSW2_ptr(RSW2_ptr), .rptr(rptr),
.wclk(wclk), .wrst_n(wrst_n)
);
sync_W2R sync_w2r (
.WSR2_ptr(WSR2_ptr), .wptr(wptr),
.rclk(rclk), .rrst_n(rrst_n)
);
// FIFO memory
fifomem #(DSIZE, ASIZE) fifomem_inst (
.rdata(rdata),
.wdata(wdata),
.raddr(raddr),
.waddr(waddr),
.wclken(wclken),
.wclk(wclk),
.rclken(rclken),
.rclk(rclk)
);
// Empty / full logic
rptr_empty #(.ASIZE(ASIZE)) rptr_empty_inst (
.rempty(rempty), .raddr(raddr), .rptr(rptr),
.WSR2_ptr(WSR2_ptr), .rinc(rinc),
.rclk(rclk), .rrst_n(rrst_n)
);
wptr_full #(.ASIZE(ASIZE)) wptr_full_inst (
.wfull(wfull), .waddr(waddr), .wptr(wptr),
.RSW2_ptr(RSW2_ptr), .winc(winc),
.wclk(wclk), .wrst_n(wrst_n)
);
wire _unused = &{ena,uio_in[5],uio_in[2:0],rst_n};
endmodule
module wptr_full #(parameter ASIZE = 4)(
output reg [ASIZE:0] wptr,
output [ASIZE-1:0] waddr,
output reg wfull,
input [ASIZE:0] RSW2_ptr,
input wclk,
input wrst_n,
input winc
);
reg [ASIZE:0] wbin;
wire [ASIZE:0] wgraynext, wbinnext;
wire wfull_val;
// Binary and Gray pointer update
always @(posedge wclk or negedge wrst_n)
if (!wrst_n)
{wbin, wptr} <= 0;
else
{wbin, wptr} <= {wbinnext, wgraynext};
// Write address for memory access
assign waddr = wbin[ASIZE-1:0];
assign wbinnext = wbin + {4'h0,(winc & ~wfull)};
assign wgraynext = (wbinnext >> 1) ^ wbinnext;
// Full condition (Cummings method)
assign wfull_val = (wgraynext == {~RSW2_ptr[ASIZE:ASIZE-1], RSW2_ptr[ASIZE-2:0]});
// wfull update
always @(posedge wclk or negedge wrst_n)
if (!wrst_n)
wfull <= 1'b0;
else
wfull <= wfull_val;
endmodule
module sync_W2R #(parameter ASIZE = 4)(
output reg [ASIZE:0] WSR2_ptr,
input [ASIZE:0] wptr,
input rclk,
input rrst_n
);
reg [ASIZE:0] WSR1_ptr;
always @(posedge rclk or negedge rrst_n)
if (!rrst_n)
{WSR2_ptr, WSR1_ptr} <= 0;
else
{WSR2_ptr, WSR1_ptr} <= {WSR1_ptr, wptr};
endmodule
module sync_R2W #(parameter ASIZE = 4)(
output reg [ASIZE:0] RSW2_ptr,
input [ASIZE:0] rptr,
input wclk,
input wrst_n
);
reg [ASIZE:0] RSW1_ptr;
always @(posedge wclk or negedge wrst_n)
if (!wrst_n)
{RSW2_ptr, RSW1_ptr} <= 0;
else
{RSW2_ptr, RSW1_ptr} <= {RSW1_ptr, rptr};
endmodule
module rptr_empty #(parameter ASIZE = 4)(
output reg [ASIZE:0] rptr,
output [ASIZE-1:0] raddr,
output reg rempty,
input [ASIZE:0] WSR2_ptr,
input rclk,
input rrst_n,
input rinc
);
reg [ASIZE:0] rbin;
wire [ASIZE:0] rgraynext, rbinnext;
wire rempty_val;
// Binary and Gray pointer update
always @(posedge rclk or negedge rrst_n)
if (!rrst_n)
{rbin, rptr} <= 0;
else
{rbin, rptr} <= {rbinnext, rgraynext};
//memory
assign raddr = rbin[ASIZE-1:0];
assign rbinnext = rbin + {4'h0,(rinc & ~rempty)};
assign rgraynext = (rbinnext >> 1) ^ rbinnext;
//empty cond
assign rempty_val = (rgraynext == WSR2_ptr);
// rempty update
always @(posedge rclk or negedge rrst_n)
if (!rrst_n)
rempty <= 1'b1; // FIFO is empty after reset
else
rempty <= rempty_val;
endmodule
module fifomem #(parameter DSIZE = 8,parameter ASIZE =4)
(output reg [DSIZE-1:0] rdata,
input [DSIZE-1:0] wdata,
input [ASIZE-1:0] raddr,waddr,
input wclken,wclk,rclken,rclk
);
localparam DEPTH = 1<<ASIZE;
reg [DSIZE-1:0] mem [0:DEPTH-1];
always@(posedge wclk)
if(wclken)
mem[waddr]<=wdata;
always@(posedge rclk)
if(rclken)
rdata <= mem[raddr];
endmodule
module clk_div(
input wire clk, // 100 MHz input clock
input wire r_rst, // active-high reset for rclk
input wire w_rst, // active-high reset for wclk
output reg wclk, // 50 MHz (÷2)
output reg rclk // ~33.3 MHz (÷3)
);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
| module clk_div(
input wire clk, // 100 MHz input clock
input wire r_rst, // active-high reset for rclk
input wire w_rst, // active-high reset for wclk
output reg wclk, // 50 MHz (÷2)
output reg rclk // ~33.3 MHz (÷3)
);
// Divide-by-2 for 50 MHz
always @(posedge clk or negedge w_rst) begin
if (!w_rst)
wclk <= 1'b0;
else
wclk <= ~wclk;
end
// Divide-by-3 for ~33.3 MHz
reg [1:0] rcount;
always @(posedge clk or negedge r_rst) begin
if (!r_rst) begin
rcount <= 0;
rclk <= 1'b0;
end else begin
rcount <= (rcount == 2) ? 0 : rcount + 1;
rclk <= (rcount < 1); // high for 1 cycle, low for 2 cycles
end
end
endmodule |
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