EdgeFirst
/

yolo26-det

@@ -102,45 +102,45 @@ Row conventions in the table below:
 - **Decoder variants.** EdgeFirst ships three INT8 split-decoders. The table headlines the accuracy-recovering ones: **smart** (per-tensor rescaling — best accuracy, extra CPU ops add some latency) and, where a smart run is absent, **logical** (the latency-optimized default — no CPU overhead, slightly lower accuracy). The **combined** decoder is the *standard-quantization baseline* (equivalent to typical single-scale INT8, and how the reference numbers are produced); it loses the most accuracy — especially on segmentation, where box/mask dynamic range collapses under one scale — so it is published only as a downloadable reference artifact and in the metrics export, never headlined here. Smart and logical exist precisely to recover that loss. Full converter documentation: [EdgeFirst model conversion](https://doc.edgefirst.ai/latest/models/conversion/) — these are the converters used by this Model Zoo and the EdgeFirst Performance Index report.
 - **Platform-label suffixes.** `(FRDM)` / `(Phytec)` name the NXP i.MX 95 development board a session ran on. `— latency` / `— throughput` mark the two pipeline configurations the NXP i.MX 95 Neutron and NXP Ara240 targets run: the **latency** pipeline runs inference serially for the lowest per-frame latency; the **throughput** pipeline runs multiple inference workers for the highest FPS, which raises per-call inference time in exchange. Rows with neither suffix run a single pipeline.
 - **End-to-end (ms)** is the sequential per-image latency of the compute pipeline — preprocess → inference → postprocess. Image acquisition (camera or file load + JPEG decode) overlaps these stages and is excluded from this figure.
-- **Realized FPS vs Theoretical FPS.** **Realized FPS** is the *measured* steady-state throughput — the rate at which final results are actually delivered over the full validation pipeline. It normally exceeds `1000 / end-to-end` because the runtime overlaps stages across frames, and it is the **true, priority number**. **Theoretical FPS** (shown with a `~`) is the accelerator's **core** ceiling — `1000 / device-compute-time`, the rate the NPU/DNPU could sustain *if it were the only bottleneck* — so it is a **possibly-achievable note, not a claim**. It is read from the isolated device-compute stage, which (unlike the host capture/preprocess stages, whose measured time inflates when the pipeline is backpressured) is stable and load-independent. Whether a deployment approaches it depends on the surrounding pipeline, and two levers dominate: (1) **host bottlenecks** — these validation runs decode a JPEG per image, whereas a live **camera pipeline** skips that decode and can run closer to the ceiling; and (2) **confidence threshold** — validation runs at `0.001` to capture every detection for mAP, which makes NMS/decode heavy, while a deployment threshold of `0.25–0.75` produces far fewer candidate boxes and lighter postprocessing, raising realized FPS toward the ceiling.
-| Size | Platform | mAP@0.5 | Δ vs FP32 (pp) | mAP@0.5-0.95 | Inference (ms) | End-to-end (ms) | Realized FPS | Theoretical FPS | Source |
-|------|----------|---------|----------------|--------------|----------------|-----------------|--------------|-----------------|--------|
-| Nano | ONNX FP32 (Intel Core i9-13900F · 32-core) | 55.03% | -0.01 | 39.70% | 29.24 | 40.70 | 93.3 | ~103 | [v-a48](https://edgefirst.studio/public/validation/v-a48/details?mode=charts) |
-| Nano | ONNX FP32 (CUDA) | 55.04% | ref | 39.69% | 7.89 | 13.05 | 356.6 | ~507 | [v-a8a](https://edgefirst.studio/public/validation/v-a8a/details?mode=charts) |
-| Nano | ONNX FP16 (CUDA) | 55.04% | +0.00 | 39.65% | 6.33 | 11.62 | 435.5 | ~540 | [v-a9f](https://edgefirst.studio/public/validation/v-a9f/details?mode=charts) |
-| Nano | Apple M2 Max — CoreML Neural Engine (FP16) | 54.60% | -0.44 | 39.35% | 1.78 | 5.23 | 800.4 | ~1121 | [v-9c7](https://edgefirst.studio/public/validation/v-9c7/details?mode=charts) |
-| Nano | Apple M2 Max — CoreML Metal GPU (FP16) | 54.59% | -0.45 | 39.36% | 6.45 | 9.93 | 408.8 | ~465 | [v-9c8](https://edgefirst.studio/public/validation/v-9c8/details?mode=charts) |
-| Nano | Apple M2 Max — CoreML CPU (FP16) | 54.58% | -0.46 | 39.32% | 14.56 | 18.50 | 128.3 | ~137 | [v-9ca](https://edgefirst.studio/public/validation/v-9ca/details?mode=charts) |
-| Nano | NXP i.MX 8M Plus + VeriSilicon NPU (FRDM) | 50.07% | -4.97 | 32.39% | 104.74 | 147.11 | 8.6 | ~10 | [v-8b7](https://edgefirst.studio/public/validation/v-8b7/details?mode=charts) |
 | Nano | NXP i.MX 95 + eIQ Neutron NPU (FRDM) — latency | In progress | — | — | — | — | — | — | [v-94e](https://edgefirst.studio/public/validation/v-94e/details?mode=charts) |
 | Nano | NXP i.MX 95 + eIQ Neutron NPU (FRDM) — throughput | In progress | — | — | — | — | — | — | [v-950](https://edgefirst.studio/public/validation/v-950/details?mode=charts) |
-| Nano | NXP Ara240 (FRDM) — latency | 51.36% | -3.68 | 34.67% | 6.20 | 18.12 | 132.4 | ~161 | [v-a16](https://edgefirst.studio/public/validation/v-a16/details?mode=charts) |
 | Nano | NXP Ara240 (FRDM) — throughput | 51.35% | -3.69 | 34.65% | 6.42 | 22.23 | 177.0 | ~324 | [v-a17](https://edgefirst.studio/public/validation/v-a17/details?mode=charts) |
-| Nano | Raspberry Pi 5 + Hailo-8L NPU | 52.72% | -2.32 | 36.61% | 21.40 | 33.45 | 45.8 | ~47 | [v-8dd](https://edgefirst.studio/public/validation/v-8dd/details?mode=charts) |
-| Nano | NVIDIA Jetson Orin Nano (TensorRT FP16) | 55.13% | +0.09 | 39.71% | 9.71 | 24.06 | 251.2 | ~276 | [v-918](https://edgefirst.studio/public/validation/v-918/details?mode=charts) |
-| Small | ONNX FP32 (Intel Core i9-13900F · 32-core) | 63.53% | -0.01 | 47.12% | 77.17 | 89.27 | 35.8 | ~39 | [v-a4f](https://edgefirst.studio/public/validation/v-a4f/details?mode=charts) |
-| Small | ONNX FP32 (CUDA) | 63.54% | ref | 47.12% | 15.40 | 20.83 | 205.7 | ~260 | [v-a91](https://edgefirst.studio/public/validation/v-a91/details?mode=charts) |
-| Small | ONNX FP16 (CUDA) | 63.53% | -0.01 | 47.09% | 10.49 | 16.07 | 294.9 | ~381 | [v-aa6](https://edgefirst.studio/public/validation/v-aa6/details?mode=charts) |
-| Small | Apple M2 Max — CoreML Neural Engine (FP16) | 62.58% | -0.96 | 46.31% | 5.40 | 8.82 | 321.2 | ~370 | [v-9d3](https://edgefirst.studio/public/validation/v-9d3/details?mode=charts) |
-| Small | Apple M2 Max — CoreML Metal GPU (FP16) | 62.60% | -0.94 | 46.37% | 15.09 | 18.89 | 187.6 | ~199 | [v-9d4](https://edgefirst.studio/public/validation/v-9d4/details?mode=charts) |
-| Small | Apple M2 Max — CoreML CPU (FP16) | 62.56% | -0.98 | 46.31% | 31.28 | 35.25 | 61.6 | ~64 | [v-9d5](https://edgefirst.studio/public/validation/v-9d5/details?mode=charts) |
 | Small | NXP i.MX 8M Plus + VeriSilicon NPU (FRDM) | 58.83% | -4.71 | 39.24% | 207.31 | 249.29 | 4.6 | ~5 | [v-928](https://edgefirst.studio/public/validation/v-928/details?mode=charts) |
-| Small | NXP Ara240 (FRDM) — latency | 59.00% | -4.54 | 41.07% | 10.35 | 22.16 | 85.9 | ~97 | [v-a24](https://edgefirst.studio/public/validation/v-a24/details?mode=charts) |
 | Small | NXP Ara240 (FRDM) — throughput | 58.98% | -4.56 | 41.05% | 10.51 | 24.06 | 137.6 | ~138 | [v-a25](https://edgefirst.studio/public/validation/v-a25/details?mode=charts) |
-| Small | Raspberry Pi 5 + Hailo-8L NPU | 59.61% | -3.93 | 42.39% | 47.35 | 60.97 | 20.4 | ~21 | [v-8ea](https://edgefirst.studio/public/validation/v-8ea/details?mode=charts) |
-| Small | NVIDIA Jetson Orin Nano (TensorRT FP16) | 63.56% | +0.02 | 47.14% | 24.76 | 36.73 | 155.0 | ~162 | [v-920](https://edgefirst.studio/public/validation/v-920/details?mode=charts) |
-| Medium | ONNX FP32 (Intel Core i9-13900F · 32-core) | 68.88% | +0.00 | 51.88% | 233.65 | 245.95 | 12.2 | ~13 | [v-a56](https://edgefirst.studio/public/validation/v-a56/details?mode=charts) |
-| Medium | ONNX FP32 (CUDA) | 68.88% | ref | 51.87% | 39.74 | 45.15 | 88.6 | ~101 | [v-a98](https://edgefirst.studio/public/validation/v-a98/details?mode=charts) |
-| Medium | ONNX FP16 (CUDA) | 68.87% | -0.01 | 51.83% | 21.99 | 27.90 | 154.0 | ~182 | [v-aad](https://edgefirst.studio/public/validation/v-aad/details?mode=charts) |
-| Medium | Apple M2 Max — CoreML Neural Engine (FP16) | 67.22% | -1.66 | 50.44% | 18.35 | 22.44 | 103.8 | ~109 | [v-9d6](https://edgefirst.studio/public/validation/v-9d6/details?mode=charts) |
-| Medium | Apple M2 Max — CoreML Metal GPU (FP16) | 67.22% | -1.66 | 50.45% | 41.00 | 45.61 | 71.0 | ~73 | [v-9d7](https://edgefirst.studio/public/validation/v-9d7/details?mode=charts) |
 | Medium | Apple M2 Max — CoreML CPU (FP16) | 67.21% | -1.67 | 50.39% | 65.90 | 70.04 | 29.8 | ~30 | [v-9d8](https://edgefirst.studio/public/validation/v-9d8/details?mode=charts) |
 | Medium | NXP i.MX 8M Plus + VeriSilicon NPU (FRDM) | 10.96% | -57.92 ⚠ | 7.32% | 359.03 | 401.07 | 2.7 | ~3 | [v-a43](https://edgefirst.studio/public/validation/v-a43/details?mode=charts) |
-| Medium | NXP Ara240 (FRDM) — latency | 63.23% | -5.65 | 43.63% | 24.39 | 36.29 | 39.0 | ~41 | [v-a32](https://edgefirst.studio/public/validation/v-a32/details?mode=charts) |
 | Medium | NXP Ara240 (FRDM) — throughput | 63.21% | -5.67 | 43.62% | 24.44 | 37.10 | 46.8 | ~47 | [v-a33](https://edgefirst.studio/public/validation/v-a33/details?mode=charts) |
 | Medium | Raspberry Pi 5 + Hailo-8L NPU | 64.12% | -4.76 | 45.88% | 88.30 | 102.16 | 11.0 | ~11 | [v-912](https://edgefirst.studio/public/validation/v-912/details?mode=charts) |
-| Medium | NVIDIA Jetson Orin Nano (TensorRT FP16) | 68.88% | +0.00 | 51.80% | 50.39 | 63.74 | 76.8 | ~79 | [v-929](https://edgefirst.studio/public/validation/v-929/details?mode=charts) |
 > **⚠ Below expectations — under investigation.** The rows marked ⚠ above measure more than 10 percentage points below the same training session's float reference: the model accuracy on that platform is below our expectations. We publish the measured numbers rather than hiding them, and we are investigating the results to make improvements — the next snapshot of this card will reflect any recovered accuracy.
@@ -157,7 +157,7 @@ These results are produced by the EdgeFirst on-target validation pipeline:
 Inference latency is reported as the on-accelerator inference time. End-to-end latency is the sequential per-image latency across the compute pipeline — preprocessing, inference, and postprocessing; image acquisition (file or camera load and JPEG decode) overlaps these stages and is excluded from this figure.
-Two throughput figures are reported. **Realized FPS** is the *measured* steady-state rate at which final results are emitted, computed from the Perfetto trace as `(N-1) / (t_last - t_first)` over the warmup-trimmed steady-state region; it is the true, priority number and generally exceeds `1000 / end-to-end` because the runtime overlaps stages across frames. **Theoretical FPS** is the accelerator's **core** ceiling — `1000 / device-compute-time`, i.e. the throughput if the accelerator were the *only* bottleneck. It is taken from the isolated device-compute stage (on transfer-split runtimes the trace separates host↔device transfers from device compute), which is load-independent — unlike the host capture/preprocess service times, whose measured cost inflates under pipeline backpressure (the same 5000 JPEGs cost ~7.8 ms/frame serialized but far more under throughput backpressure), so the slowest-stage figure would *understate* a fast accelerator. It is a possibly-achievable ceiling, not a measured result: reaching it depends on the deployment pipeline. A validation run decodes a JPEG per image and evaluates at a `0.001` confidence threshold (to capture every detection for mAP), both of which load the host and postprocess stages; a production camera pipeline (no JPEG decode) at a deployment threshold of `0.25–0.75` (far fewer candidate boxes through NMS) moves realized throughput toward the theoretical ceiling.
 See [EdgeFirst Studio](https://edgefirst.studio) for the full validation pipeline.

 - **Decoder variants.** EdgeFirst ships three INT8 split-decoders. The table headlines the accuracy-recovering ones: **smart** (per-tensor rescaling — best accuracy, extra CPU ops add some latency) and, where a smart run is absent, **logical** (the latency-optimized default — no CPU overhead, slightly lower accuracy). The **combined** decoder is the *standard-quantization baseline* (equivalent to typical single-scale INT8, and how the reference numbers are produced); it loses the most accuracy — especially on segmentation, where box/mask dynamic range collapses under one scale — so it is published only as a downloadable reference artifact and in the metrics export, never headlined here. Smart and logical exist precisely to recover that loss. Full converter documentation: [EdgeFirst model conversion](https://doc.edgefirst.ai/latest/models/conversion/) — these are the converters used by this Model Zoo and the EdgeFirst Performance Index report.
 - **Platform-label suffixes.** `(FRDM)` / `(Phytec)` name the NXP i.MX 95 development board a session ran on. `— latency` / `— throughput` mark the two pipeline configurations the NXP i.MX 95 Neutron and NXP Ara240 targets run: the **latency** pipeline runs inference serially for the lowest per-frame latency; the **throughput** pipeline runs multiple inference workers for the highest FPS, which raises per-call inference time in exchange. Rows with neither suffix run a single pipeline.
 - **End-to-end (ms)** is the sequential per-image latency of the compute pipeline — preprocess → inference → postprocess. Image acquisition (camera or file load + JPEG decode) overlaps these stages and is excluded from this figure.
+- **Realized FPS vs Core-throughput ceiling (FPS).** **Realized FPS** is the *measured* steady-state throughput — the rate at which final results are actually delivered over the full validation pipeline. It normally exceeds `1000 / end-to-end` because the runtime overlaps stages across frames, and it is the **true, priority number**. **Core-throughput ceiling (FPS)** (shown with a `~`) is the accelerator's **core** ceiling — `1000 / device-compute-time`, the rate the NPU/DNPU could sustain *if it were the only bottleneck* — so it is a **possibly-achievable note, not a claim**. It is read from the isolated device-compute stage, which (unlike the host capture/preprocess stages, whose measured time inflates when the pipeline is backpressured) is stable and load-independent. Whether a deployment approaches it depends on the surrounding pipeline, and two levers dominate: (1) **host bottlenecks** — these validation runs decode a JPEG per image, whereas a live **camera pipeline** skips that decode and can run closer to the ceiling; and (2) **confidence threshold** — validation runs at `0.001` to capture every detection for mAP, which makes NMS/decode heavy, while a deployment threshold of `0.25–0.75` produces far fewer candidate boxes and lighter postprocessing, raising realized FPS toward the ceiling.
+| Size | Platform | mAP@0.5 | Δ vs FP32 (pp) | mAP@0.5-0.95 | Inference (ms) | End-to-end (ms) | Realized FPS | Core-throughput ceiling (FPS) | Source |
+|------|----------|---------|----------------|--------------|----------------|-----------------|--------------|-------------------------------|--------|
+| Nano | ONNX FP32 (Intel Core i9-13900F · 32-core) | 55.03% | -0.01 | 39.70% | 29.24 | 40.70 | 93.3 | ~93 | [v-a48](https://edgefirst.studio/public/validation/v-a48/details?mode=charts) |
+| Nano | ONNX FP32 (CUDA) | 55.04% | ref | 39.69% | 7.89 | 13.05 | 356.6 | ~356 | [v-a8a](https://edgefirst.studio/public/validation/v-a8a/details?mode=charts) |
+| Nano | ONNX FP16 (CUDA) | 55.04% | +0.00 | 39.65% | 6.33 | 11.62 | 435.5 | ~435 | [v-a9f](https://edgefirst.studio/public/validation/v-a9f/details?mode=charts) |
+| Nano | Apple M2 Max — CoreML Neural Engine (FP16) | 54.60% | -0.44 | 39.35% | 1.78 | 5.23 | 800.4 | ~731 | [v-9c7](https://edgefirst.studio/public/validation/v-9c7/details?mode=charts) |
+| Nano | Apple M2 Max — CoreML Metal GPU (FP16) | 54.59% | -0.45 | 39.36% | 6.45 | 9.93 | 408.8 | ~408 | [v-9c8](https://edgefirst.studio/public/validation/v-9c8/details?mode=charts) |
+| Nano | Apple M2 Max — CoreML CPU (FP16) | 54.58% | -0.46 | 39.32% | 14.56 | 18.50 | 128.3 | ~128 | [v-9ca](https://edgefirst.studio/public/validation/v-9ca/details?mode=charts) |
+| Nano | NXP i.MX 8M Plus + VeriSilicon NPU (FRDM) | 50.07% | -4.97 | 32.39% | 104.74 | 147.11 | 8.6 | ~9 | [v-8b7](https://edgefirst.studio/public/validation/v-8b7/details?mode=charts) |
 | Nano | NXP i.MX 95 + eIQ Neutron NPU (FRDM) — latency | In progress | — | — | — | — | — | — | [v-94e](https://edgefirst.studio/public/validation/v-94e/details?mode=charts) |
 | Nano | NXP i.MX 95 + eIQ Neutron NPU (FRDM) — throughput | In progress | — | — | — | — | — | — | [v-950](https://edgefirst.studio/public/validation/v-950/details?mode=charts) |
+| Nano | NXP Ara240 (FRDM) — latency | 51.36% | -3.68 | 34.67% | 6.20 | 18.12 | 132.4 | ~136 | [v-a16](https://edgefirst.studio/public/validation/v-a16/details?mode=charts) |
 | Nano | NXP Ara240 (FRDM) — throughput | 51.35% | -3.69 | 34.65% | 6.42 | 22.23 | 177.0 | ~324 | [v-a17](https://edgefirst.studio/public/validation/v-a17/details?mode=charts) |
+| Nano | Raspberry Pi 5 + Hailo-8L NPU | 52.72% | -2.32 | 36.61% | 21.40 | 33.45 | 45.8 | ~46 | [v-8dd](https://edgefirst.studio/public/validation/v-8dd/details?mode=charts) |
+| Nano | NVIDIA Jetson Orin Nano (TensorRT FP16) | 55.13% | +0.09 | 39.71% | 9.71 | 24.06 | 251.2 | ~251 | [v-918](https://edgefirst.studio/public/validation/v-918/details?mode=charts) |
+| Small | ONNX FP32 (Intel Core i9-13900F · 32-core) | 63.53% | -0.01 | 47.12% | 77.17 | 89.27 | 35.8 | ~36 | [v-a4f](https://edgefirst.studio/public/validation/v-a4f/details?mode=charts) |
+| Small | ONNX FP32 (CUDA) | 63.54% | ref | 47.12% | 15.40 | 20.83 | 205.7 | ~206 | [v-a91](https://edgefirst.studio/public/validation/v-a91/details?mode=charts) |
+| Small | ONNX FP16 (CUDA) | 63.53% | -0.01 | 47.09% | 10.49 | 16.07 | 294.9 | ~295 | [v-aa6](https://edgefirst.studio/public/validation/v-aa6/details?mode=charts) |
+| Small | Apple M2 Max — CoreML Neural Engine (FP16) | 62.58% | -0.96 | 46.31% | 5.40 | 8.82 | 321.2 | ~322 | [v-9d3](https://edgefirst.studio/public/validation/v-9d3/details?mode=charts) |
+| Small | Apple M2 Max — CoreML Metal GPU (FP16) | 62.60% | -0.94 | 46.37% | 15.09 | 18.89 | 187.6 | ~188 | [v-9d4](https://edgefirst.studio/public/validation/v-9d4/details?mode=charts) |
+| Small | Apple M2 Max — CoreML CPU (FP16) | 62.56% | -0.98 | 46.31% | 31.28 | 35.25 | 61.6 | ~62 | [v-9d5](https://edgefirst.studio/public/validation/v-9d5/details?mode=charts) |
 | Small | NXP i.MX 8M Plus + VeriSilicon NPU (FRDM) | 58.83% | -4.71 | 39.24% | 207.31 | 249.29 | 4.6 | ~5 | [v-928](https://edgefirst.studio/public/validation/v-928/details?mode=charts) |
+| Small | NXP Ara240 (FRDM) — latency | 59.00% | -4.54 | 41.07% | 10.35 | 22.16 | 85.9 | ~87 | [v-a24](https://edgefirst.studio/public/validation/v-a24/details?mode=charts) |
 | Small | NXP Ara240 (FRDM) — throughput | 58.98% | -4.56 | 41.05% | 10.51 | 24.06 | 137.6 | ~138 | [v-a25](https://edgefirst.studio/public/validation/v-a25/details?mode=charts) |
+| Small | Raspberry Pi 5 + Hailo-8L NPU | 59.61% | -3.93 | 42.39% | 47.35 | 60.97 | 20.4 | ~20 | [v-8ea](https://edgefirst.studio/public/validation/v-8ea/details?mode=charts) |
+| Small | NVIDIA Jetson Orin Nano (TensorRT FP16) | 63.56% | +0.02 | 47.14% | 24.76 | 36.73 | 155.0 | ~155 | [v-920](https://edgefirst.studio/public/validation/v-920/details?mode=charts) |
+| Medium | ONNX FP32 (Intel Core i9-13900F · 32-core) | 68.88% | +0.00 | 51.88% | 233.65 | 245.95 | 12.2 | ~12 | [v-a56](https://edgefirst.studio/public/validation/v-a56/details?mode=charts) |
+| Medium | ONNX FP32 (CUDA) | 68.88% | ref | 51.87% | 39.74 | 45.15 | 88.6 | ~89 | [v-a98](https://edgefirst.studio/public/validation/v-a98/details?mode=charts) |
+| Medium | ONNX FP16 (CUDA) | 68.87% | -0.01 | 51.83% | 21.99 | 27.90 | 154.0 | ~154 | [v-aad](https://edgefirst.studio/public/validation/v-aad/details?mode=charts) |
+| Medium | Apple M2 Max — CoreML Neural Engine (FP16) | 67.22% | -1.66 | 50.44% | 18.35 | 22.44 | 103.8 | ~104 | [v-9d6](https://edgefirst.studio/public/validation/v-9d6/details?mode=charts) |
+| Medium | Apple M2 Max — CoreML Metal GPU (FP16) | 67.22% | -1.66 | 50.45% | 41.00 | 45.61 | 71.0 | ~71 | [v-9d7](https://edgefirst.studio/public/validation/v-9d7/details?mode=charts) |
 | Medium | Apple M2 Max — CoreML CPU (FP16) | 67.21% | -1.67 | 50.39% | 65.90 | 70.04 | 29.8 | ~30 | [v-9d8](https://edgefirst.studio/public/validation/v-9d8/details?mode=charts) |
 | Medium | NXP i.MX 8M Plus + VeriSilicon NPU (FRDM) | 10.96% | -57.92 ⚠ | 7.32% | 359.03 | 401.07 | 2.7 | ~3 | [v-a43](https://edgefirst.studio/public/validation/v-a43/details?mode=charts) |
+| Medium | NXP Ara240 (FRDM) — latency | 63.23% | -5.65 | 43.63% | 24.39 | 36.29 | 39.0 | ~39 | [v-a32](https://edgefirst.studio/public/validation/v-a32/details?mode=charts) |
 | Medium | NXP Ara240 (FRDM) — throughput | 63.21% | -5.67 | 43.62% | 24.44 | 37.10 | 46.8 | ~47 | [v-a33](https://edgefirst.studio/public/validation/v-a33/details?mode=charts) |
 | Medium | Raspberry Pi 5 + Hailo-8L NPU | 64.12% | -4.76 | 45.88% | 88.30 | 102.16 | 11.0 | ~11 | [v-912](https://edgefirst.studio/public/validation/v-912/details?mode=charts) |
+| Medium | NVIDIA Jetson Orin Nano (TensorRT FP16) | 68.88% | +0.00 | 51.80% | 50.39 | 63.74 | 76.8 | ~77 | [v-929](https://edgefirst.studio/public/validation/v-929/details?mode=charts) |
 > **⚠ Below expectations — under investigation.** The rows marked ⚠ above measure more than 10 percentage points below the same training session's float reference: the model accuracy on that platform is below our expectations. We publish the measured numbers rather than hiding them, and we are investigating the results to make improvements — the next snapshot of this card will reflect any recovered accuracy.
 Inference latency is reported as the on-accelerator inference time. End-to-end latency is the sequential per-image latency across the compute pipeline — preprocessing, inference, and postprocessing; image acquisition (file or camera load and JPEG decode) overlaps these stages and is excluded from this figure.
+Two throughput figures are reported. **Realized FPS** is the *measured* steady-state rate at which final results are emitted, measured directly from the profiler's per-frame result-emission timestamps over the steady-state stream — trace-independent; the Perfetto trace's own FPS is used only as a fallback on sessions where that scalar isn't available. It is the true, priority number and generally exceeds `1000 / end-to-end` because the runtime overlaps stages across frames. **Core-throughput ceiling (FPS)** is the accelerator's **core** ceiling — `1000 / device-compute-time`, i.e. the throughput if the accelerator were the *only* bottleneck. It is taken from the isolated device-compute stage (on transfer-split runtimes the trace separates host↔device transfers from device compute), which is load-independent — unlike the host capture/preprocess service times, whose measured cost inflates under pipeline backpressure (the same 5000 JPEGs cost ~7.8 ms/frame serialized but far more under throughput backpressure), so the slowest-stage figure would *understate* a fast accelerator. It is a possibly-achievable ceiling, not a measured result: reaching it depends on the deployment pipeline. A validation run decodes a JPEG per image and evaluates at a `0.001` confidence threshold (to capture every detection for mAP), both of which load the host and postprocess stages; a production camera pipeline (no JPEG decode) at a deployment threshold of `0.25–0.75` (far fewer candidate boxes through NMS) moves realized throughput toward the core-throughput ceiling.
 See [EdgeFirst Studio](https://edgefirst.studio) for the full validation pipeline.