name: CI

on:
  push:
    branches: [main]
  pull_request:
  workflow_dispatch:

permissions:
  contents: read

concurrency:
  group: ci-${{ github.ref }}
  cancel-in-progress: true

jobs:
  hdl:
    name: RTL lint and simulation
    runs-on: ubuntu-24.04
    steps:
      - uses: actions/checkout@v4
      - name: Install simulators
        run: sudo apt-get update && sudo apt-get install -y --no-install-recommends iverilog verilator
      - name: Compact accelerator
        run: make lint sim
      - name: Compact accelerator, extra random seeds
        run: for s in 2 3 4; do make sim-icarus SEED=$s OPS=3000; done
      - name: bit_accelerator v2
        run: make -C bit_accelerator lint sim

  formal:
    name: Why3 proofs
    runs-on: ubuntu-24.04
    steps:
      - uses: actions/checkout@v4
      - name: Install Why3 and Z3
        run: |
          sudo apt-get update && sudo apt-get install -y --no-install-recommends why3 z3
          why3 config detect
      - name: Compact accelerator proofs
        run: make formal
      - name: bit_accelerator v2 proofs
        run: make -C bit_accelerator formal

  spice:
    name: SPICE timing model
    runs-on: ubuntu-24.04
    steps:
      - uses: actions/checkout@v4
      - run: sudo apt-get update && sudo apt-get install -y --no-install-recommends ngspice
      - run: make spice

  gpu:
    name: Rust OpenCL crate (gpu/)
    runs-on: ubuntu-24.04
    defaults:
      run:
        working-directory: gpu
    steps:
      - uses: actions/checkout@v4
      - name: Install OpenCL (PoCL CPU device)
        run: |
          sudo apt-get update
          sudo apt-get install -y --no-install-recommends pocl-opencl-icd ocl-icd-opencl-dev clinfo
          clinfo -l
      - uses: dtolnay/rust-toolchain@stable
        with:
          components: rustfmt, clippy
      - uses: Swatinem/rust-cache@v2
        with:
          workspaces: gpu
      - run: cargo fmt --check
      - run: cargo clippy --all-targets -- -D warnings
      # Serial: PoCL 5.0 can abort (pocl_release_dlhandle_cache assertion) when
      # several OpenCL contexts are released from different threads at once.
      - run: cargo test
        env:
          RUST_TEST_THREADS: "1"
      - run: cargo run --quiet

  fpga:
    name: FPGA build (lint, UART testbench, host co-simulation, bitstreams)
    runs-on: ubuntu-24.04
    steps:
      - uses: actions/checkout@v4
      - name: Install FPGA toolchain
        run: |
          sudo apt-get update
          sudo apt-get install -y --no-install-recommends iverilog verilator yosys \
            nextpnr-ice40 nextpnr-ecp5 fpga-icestorm fpga-trellis
      - uses: dtolnay/rust-toolchain@stable
        with:
          components: rustfmt, clippy
      - uses: Swatinem/rust-cache@v2
        with:
          workspaces: fpga/host
      - run: make -C fpga lint sim host cosim icebreaker ulx3s
      - uses: actions/upload-artifact@v4
        with:
          name: bitstreams
          path: |
            fpga/build/icebreaker.bin
            fpga/build/ulx3s.bit
            fpga/build/*_pnr.log

  fpga-gate-level:
    name: FPGA gate-level simulation (${{ matrix.arch }})
    runs-on: ubuntu-24.04
    strategy:
      matrix:
        arch: [ice40, ecp5]
    steps:
      - uses: actions/checkout@v4
      - run: sudo apt-get update && sudo apt-get install -y --no-install-recommends iverilog yosys
      - run: make -C fpga gl-sim-${{ matrix.arch }}

  asic:
    name: sky130 synthesis and equivalence
    runs-on: ubuntu-24.04
    steps:
      - uses: actions/checkout@v4
      - run: sudo apt-get update && sudo apt-get install -y --no-install-recommends yosys
      - run: make -C asic all
      - uses: actions/upload-artifact@v4
        with:
          name: sky130-netlist
          path: |
            asic/build/bit_accelerator_sky130.v
            asic/build/area.rpt

  pcie:
    name: PCIe engine (lint, equivalence vs reference core)
    runs-on: ubuntu-24.04
    steps:
      - uses: actions/checkout@v4
      - run: sudo apt-get update && sudo apt-get install -y --no-install-recommends iverilog verilator
      # The simulation runs are independent make targets; the largest geometry takes ~6 minutes.
      - run: make -C pcie -j$(nproc) lint sim sim-verilator

  pcie-cosim:
    name: PCIe SoC generation + host co-simulation + throughput
    runs-on: ubuntu-24.04
    steps:
      - uses: actions/checkout@v4
      - run: sudo apt-get update && sudo apt-get install -y --no-install-recommends verilator
      - uses: actions/setup-python@v5
        with:
          python-version: '3.11'
      - name: Install LiteX
        run: |
          for r in m-labs/migen enjoy-digital/litex litex-hub/litex-boards enjoy-digital/litepcie \
                   enjoy-digital/litedram enjoy-digital/liteeth enjoy-digital/litescope; do
            git clone --depth 1 https://github.com/$r /tmp/$(basename $r)
            pip install -e /tmp/$(basename $r)
          done
      - run: make -C pcie soc cosim perf

  tapeout:
    name: Tiny Tapeout project (sync, RTL test)
    runs-on: ubuntu-24.04
    steps:
      - uses: actions/checkout@v4
      - run: sudo apt-get update && sudo apt-get install -y --no-install-recommends iverilog
      - run: make -C tapeout check-sync test